IRCC datasheet(25/79 Pages) SMSC

25 / 79 page

SCE CONTROLS

The IrCC SCE Registers are arranged in 7-byte

blocks. Of the eight possible register blocks, five

are used in this implementation.

The Master Block Control Register controls

access to the register blocks.

Table 13 lists all of the SCE registers in all

blocks.

Table 13 - SCE Register Addressing

BLOCK

ADDRESS

DIRECTION

R/W

Master Control

R/W

Data Register

Interrupt Identification

R/W

Interrupt Enable

Line Status (read)

Line Status Address (write)

R/W

Line Control A

R/W

Line Control B

R/W

Bus Status

R/W

SCE Configuration A

R/W

SCE Configuration B

R/W

FIFO Threshold

R/W

Consumer IR Control

R/W

Consumer IR Carrier Rate

R/W

Consumer IR Bit Rate

SMSC ID (high)

SMSC ID (low)

CHIP ID

VERSION Number

IRQ Level

DMA Channel

R/W

IrDA Control

BOF Count (high)

R/W

BOF Count (low)

R/W

Brick Wall Count (low)

R/W

BW Count (high)

Tx Data Size (high)

R/W

Tx Data Size (low)

R/W

Rx Data Size (high)

R/W

Rx Data Size (low)

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