FC3255 datasheet(13/18 Pages) FCI

13 / 18 page

Where

= the current through the switch;

D = the duty cycle or percentage of switch on-time.

and D are dependent on the type of converter. In

a boost convert,

In a flyback converter,

The switch saturation voltage, V

, is the last ma-

(CE)SAT

jor source of on-chip power loss. V

is the collec-

(CE)SAT

tor-emitter voltage of the internal NPN transistor when

it is driven into saturation by its base drive current. The

value for V

can be obtained from the specifica-

(CE)SAT

tions or from the graphs, as "Switch Saturation

Voltage." Thus,

Finally, the total on-chip power losses are

Power dissipation in a semiconductor device results in

the generation of heat in the junctions at the surface of

the chip. This heat is transferred to the surface of the

IC package, but a thermal gradient exists due to the re-

sistive properties of the package molding compound.

The magnitude of the thermal gradient is expressed in

manufacturers' data sheets as Q , or junction-to- ambi-

ent thermal resistance. The on-chip junction tempera-

ture can be calculated if Q , the air temperature near

the surface of the IC, and the on-chip power dissipation

are known.

T = T + (P Q )

D JA

where:

T = IC or FET junction temperature (°C);

T = ambient temperature (°C);

P = power dissipated by part in question(W);

= junction-to ambient thermal resistance (°C / W).

For 3255,

= 165°C / W. Once the designer

has calculated T , the question of whether the 3255

can be used in an application is settled. If T exceeds

150°C, the absolute maximum allowable junction tem-

perature, the 3255 is not suitable for that applica-

tion.

@ I

X D X

SW(AVG)

LOAD

Efficiency

D @

-V

OUT

SW(AVG)

Efficiency

OUT LOAD

D @

OUT

@ VI

X D

SAT

(CE)SAT SW

= P

+ P

BIAS

DRIVER

SAT

If T

approaches 150°C, the designer should con-

sider possible means of reducing the junction temper-

ature. Perhaps another converter topology could be

selected to reduce the switch current. Increasing the

airflow across the surface of the chip might be consid-

ered to reduce T .

Output Setting

3255 develops a 1.276 V reference (V

) from

REF

the FB pin to ground. Output voltage is set by con-

necting the FB pin to an output resistor divider (Figure

16). The FB pin bias current represents a small error

and can usually be ignored for values of R2 up to 7k.

The suggested value for R2 is 6.19k.

Circuit Layout Guidelines

In any switching power supply, circuit layout is very

important for proper operation. Rapidly switching cur-

rents combined with trace inductance generates volt-

age transitions that can cause problems. Therefore

the following guidelines should be followed in the lay-

out.

1. In boost circuits, high AC current circulates within

the loop composed of the diode, output capacitor, and

on-chip power transistor. The length of associated

traces and leads should be kept as short as possible.

In the flyback circuit, high AC current loops exist on

both sides of the transformer. On the primary side,

the loop consists of the input capacitor, transformer,

and on-chip power transistor, while the transformer,

rectifier diodes, and output capacitors form another

loop on the secondary side. Just as in the boost cir-

cuit, all traces and leads containing large AC current

should be kept short.

2. Separate the low current signal grounds from the

power grounds. Use single point grounding or ground

plane construction for the best results.

3. Locate the voltage feedback as near the IC as, pos-

sible to keep the sensitive feedback wiring short.

Connect feedback resistors to the low current analog

ground.

VOUT

VREF

OUT

(1 +

)

REF

R1 = R2 (

-1)

VOUT

1.276

Figure 16. Output Resistor Divider

FC3255 1.5A PWM Switching Regulators

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