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RT8901GS Arkusz danych(PDF) 2 Page - Richtek Technology Corporation |
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RT8901GS Arkusz danych(HTML) 2 Page - Richtek Technology Corporation |
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2 / 10 page ![]() RT8901 2 DS8901-03 October 2013 www.richtek.com © Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Timing Diagram Figure 3. Timing Sequence of Mode A Figure 4. Timing Sequence of Mode B Figure 5. Timing Sequence of Mode C VDPM VREF VFLK VGHM Duty is controlled by VFLK Discharging Time is controlled by R1 CD VCD = 5V 10VD VGH 0V High 0V Low VGH VDPM VGH VREF VFLK VGHM Duty is controlled by VFLK and C4 CD 0.9VDD 10VD VREF 0V 0V VGH Discharging Time is controlled by R1 VDPM VREF VFLK VGHM Duty is controlled by VFLK CD VCD = 3.3V 10VD VGH 0V High 0V Low VGH Discharging Time is controlled by R1 |
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