MPC7457 datasheet(7/68 Pages) FREESCALE

7 / 68 page

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441

— Thermal management facility provides software-controllable thermal management. Thermal

management is performed through the use of three supervisor-level registers and an MPC7457-specific

thermal management exception.

— Instruction cache throttling provides control of instruction fetching to limit power consumption

•

Performance monitor can be used to help debug system designs and improve software efficiency

•

In-system testability and debugging features through JTAG boundary-scan capability

•

Testability

— LSSD scan design

— IEEE 1149.1 JTAG interface

— Array built-in self test (ABIST)—factory test only

•

Reliability and serviceability

— Parity checking on system bus and L3 cache bus

— Parity checking on the L2 and L3 cache tag arrays

Comparison with the MPC7455, MPC7445, MPC7450,

MPC7451, and MPC7441

Table 1 compares the key features of the MPC7457 with the key features of the earlier MPC7455, MPC7445,

MPC7450, MPC7451, and MPC7441. To achieve a higher frequency, the number of logic levels per cycle is

reduced. Also, to achieve this higher frequency, the pipeline of the MPC7457 is extended (compared to the

MPC7400), while maintaining the same level of performance as measured by the number of instructions executed

per cycle (IPC).

Table 1. Microarchitecture Comparison

Microarchitectural Specs

MPC7457/MPC7447

MPC7455/MPC7445

MPC7450/MPC7451/

MPC7441

Basic Pipeline Functions

Logic inversions per cycle

Pipeline stages up to execute

Total pipeline stages (minimum)

Pipeline maximum instruction throughput

3 + Branch

Pipeline Resources

Instruction buffer size

Completion buffer size

Renames (integer, float, vector)

16, 16, 16

Maximum Execution Throughput

SFX

Vector

2 (any 2 of 4 units)

Scalar floating-point

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