WM8150

Production Data

w

PD Rev 3.0 November 2002

4

ELECTRICAL CHARACTERISTICS

Test Conditions

°C, MCLK = 16MHz unless otherwise stated.

PARAMETER

SYMBOLTEST

CONDITIONS

MIN

TYP

MAX

UNIT

Overall System Specification (including 12-bit ADC, PGA, Offset and CDS functions)

Full-scale input voltage range

(see Note 1)

Max Gain

Min Gain

0.30

3.22

Vp-p

Vp-p

Input signal limits (see Note 2)

0VDD

V

Full-scale transition error

Gain = 0dB;

PGA[7:0] = 07(hex)

-50

10

+50

mV

Zero-scale transition error

Gain = 0dB;

PGA[7:0] = 07(hex)

-50

10

+50

mV

Differential non-linearity

DNL

0.5

1

LSB

Integral non-linearity

INL

2

5

LSB

Total output noise

Min Gain

Max Gain

0.25

0.70

LSB rms

LSB rms

References

Upper reference voltage

VRT

2.70

V

Lower reference voltage

VRB

1.45

V

Input return bias voltage

VRX

1.55

1.65

1.75

V

Diff. reference voltage (VRT-VRB)

1.15

1.25

1.35

V

Output resistance VRT, VRB, VRX

1

Ω

VRLC/Reset-Level Clamp (RLC)

RLC switching impedance

20

50

100

Ω

VRLC short-circuit current

1.86

2

4.5

mA

VRLC output resistance

2

Ω

VRLC Hi-Z leakage current

VRLC = 0 to AVDD

1

µA

RLCDAC resolution

4bits

RLCDAC step size, RLCDAC = 0

AVDD = 5.0V

0.23

0.25

0.27

V/step

RLCDAC step size, RLCDAC = 1

0.14

0.16

0.20

V/step

RLCDAC output voltage at

code 0(hex), RLCDACRNG = 0

AVDD = 5.0V

0.34

0.39

0.44

V

RLCDAC output voltage at

code 0(hex), RLCDACRNG = 1

0.20

0.26

0.31

V

RLCDAC output voltage at

code F(hex) RLCDACRNG, = 0

AVDD = 5.0V

4.0

4.16

4.3

V

RLCDAC output voltage at

code F(hex), RLCDACRNG = 1

2.56

2.66

2.76

V

Offset DAC, Monotonicity Guaranteed

Resolution

8bits

Differential non-linearity

DNL

0.1

0.5

LSB

Integral non-linearity

INL

0.25

1

LSB

Step size

2.04

mV/step

Output voltage

Code 00(hex)

Code FF(hex)

-247

+247

-260

+260

-273

+273

mV

mV

Notes:

1.

Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input

range.

2.

Input signal limits are the limits within which the full-scale input voltage signal must lie.