AT75C310

11

Figure 10. Static Memory Read Cycle (LCD Mode, Two Wait States)

Table 9. Static Memory Read Cycle (LCD Mode, Two Wait States) Timings

Symbol

Parameter

Min (ns)

Max (ns)

t

CSLCSH

Chip Select Low to Chip Select High Time

82.0

–

Address Valid to Chip Select Low

18.0

–

t

CSHAH

Address Hold after Chip Select High

21.0

–

t

RLRH

Read Strobe Low to Read Strobe High Time

102.0

Read Strobe Low to Data Valid Time – Standard

Read Mode

–

89.0

t

RLDV2

Read Strobe Low to Data Valid Time – Early Read

Mode

–

110.0

t

CSLDV

Chip Select Low to Data Valid

–

88.0

t

AVDV

Address Valid to Data Valid

–

107.0

Address Hold after Read Strobe High

1.0

–

t

RHDH

Data Hold after Read Strobe High

0

–

t

CSHDH

Data Hold after Chip Select High

18.0

–

A

NCE3

D

NSOE

(Early Read Mode)

NSOE

(Standard Read Mode)