ECT25S40 datasheet(10/46 Pages) E-CMOS

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E-CMOS Corp. (www.ecmos.com.tw)

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4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

Status Register Protect Table

Table 5. Status Register protect table

Notes:

1.When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.

2.The One time Programfeature is available upon special order.

Write Protect Features

1.Software Protection: The Block

Protect (SEC, TB, BP2, BP1, BP0) bits define the section of the

memory array that can be read but not change.

2.Hardware Protection: /WP going low to protected the BP0~SEC bits and SRP0~1 bits.

3.Deep Power-Down: In Deep Power-Down Mode,all instructions are ignored except the Release from

deep Power-Down Mode instruction.

4.Write Enable: The Write Enable Latch(WEL) bit must be set prior to every Page Program, Sector Erase,

Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction.

SRP1

SRP0

/WP

Status Register

Description

Software

Protected

The Status Register can be written to after a Write

Enable instruction, WEL=1.(Factory Default)

Hardware

Protected

/WP=0, the Status Register locked and cannot be

written.

Hardware

Unprotected

/WP=1, the Status Register is unlocked and can be

written to after a Write Enable instruction, WEL=1.

Power Supply

Lock-Down(1)

Status Register is protected and cannot be written

to again until the next Power-Down, Power-Up

cycle.

One Time

Program(2)

Status Register is permanently protected and

cannot be written to.

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