AD9480 datasheet(7/29 Pages) AD

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AD9480

Rev. A | Page 6 of 28

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, differential clock input, DCS enabled, unless otherwise noted.

Table 4.

AD9480-250

Parameter

Temp

Test Level

Min

Typ

Max

Unit

CLOCK

Maximum Conversion Rate

Full

250

MSPS

Minimum Conversion Rate

Full

MSPS

Clock Pulse Width High (tEH)

Full

1.2

Clock Pulse Width Low (tEL)

Full

1.2

OUTPUT PARAMETERS

Valid Time (tV)1

Full

1.9

Propagation Delay (tPD)

Full

2.8

3.8

Rise Time (tR) 20% to 80%

Full

0.5

Fall Time (tF) 20% to 80%

Full

0.5

DCO Propagation Delay (tCPD)

Full

1.9

2.7

3.7

Data-to-DCO Skew (tPD − tCPD)

Full

0.1

0.6

Pipeline Latency

25°C

Cycles

APERTURE

Aperture Delay (tA)

25°C

1.5

Aperture Uncertainty (Jitter)

25°C

0.25

ps rms

1 Valid time is approximately equal to minimum tPD. CLOAD equals 5 pF maximum.

TIMING DIAGRAM

N–1

N+1

N+8

N+9

N+10

N+11

tEH

tEL

1/fS

N–8

tPD

8 CYCLES

N–7

N+1

N+2

tCPD

CLK+

CLK–

DATA

OUT

DCO–

DCO+

AIN

Figure 2. Timing Diagram

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