AD9430 datasheet(13/45 Pages) AD

13 / 45 page

AD9430

Rev. E | Page 12 of 44

Pin Number

Mnemonic

Description

CLK+

Clock Input—True.

CLK–

Clock Input—Complement.

DB0

B Port Output Data Bit (LSB).

DB1

B Port Output Data Bit.

DB2

B Port Output Data Bit.

47, 54, 62, 75, 83

DRVDD

3.3 V Digital Output Supply (3.0 V to 3.6 V).

48, 53, 61, 67, 74, 82

DRGND1

Digital Output Ground.

DB3

B Port Output Data Bit.

DB4

B Port Output Data Bit.

DB5

B Port Output Data Bit.

DB6

B Port Output Data Bit.

DB7

B Port Output Data Bit.

DB8

B Port Output Data Bit.

DB9

B Port Output Data Bit.

DB10

B Port Output Data Bit.

DB11

B Port Output Data Bit (MSB).

OR_B

B Port Overrange.

DCO–

Data Clock Output—Complement.

DCO+

Data Clock Output—True.

DA0

A Port Output Data Bit (LSB).

DA1

A Port Output Data Bit.

DA2

A Port Output Data Bit.

DA3

A Port Output Data Bit.

DA4

A Port Output Data Bit.

DA5

A Port Output Data Bit.

DA6

A Port Output Data Bit.

DA7

A Port Output Data Bit.

DA8

A Port Output Data Bit.

DA9

A Port Output Data Bit.

DA10

A Port Output Data Bit.

DA11

A Port Output Data Bit (MSB).

OR_A

A Port Overrange.

1 AGND and DRGND should be tied together to a common ground plane.

2 DS Complement (DS−); can be tied to AVDD (as recommended) or left floating with no ill effects.

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