AD9225ARSZRL datasheet(21/26 Pages) AD

21 / 26 page

–20–

AD9225

AIN (dBFS)

–15

–10

–5

100

SFDR

DUAL-TONE

(dBFS)

SNR

SINGLE-TONE

(dBc)

SFDR

SINGLE-TONE

(dBFS)

Figure 29. IF Undersampling at 70 MHz (F1 = 69.50 MHz,

F2 = 70.11 MHz, CLOCK = 25 MHz)

AIN (dBFS)

–15

–10

–5

100

SFDR

DUAL-TONE

(dBFS)

SNR

SINGLE-TONE

(dBc)

SFDR

SINGLE-TONE

(dBFS)

Figure 30. IF Undersampling at 85 MHz (F1 = 84.81 MHz,

F2 = 85.23 MHz, CLOCK = 20 MHz)

GROUNDING AND DECOUPLING

Analog and Digital Grounding

Proper grounding is essential in any high speed, high resolution

system. Multilayer printed circuit boards (PCBs) are recom-

mended to provide optimal grounding and power schemes. The

use of ground and power planes offers distinct advantages:

•The minimization of the loop area encompassed by a signal

and its return path.

•The minimization of the impedance associated with ground

and power paths.

•The inherent distributed capacitor formed by the power

plane, PCB insulation and ground plane.

These characteristics result in both a reduction of electro-

magnetic interference (EMI) and an overall improvement

in performance.

It is important to design a layout that prevents noise from cou-

pling onto the input signal. Digital signals should not be run in

parallel with input signal traces and should be routed away from

the input circuitry. While the AD9225 features separate analog

and driver ground pins, it should be treated as an analog com-

ponent. The AVSS and DRVSS pins must be joined together

directly under the AD9225. A solid ground plane under the

ADC is acceptable if the power and ground return currents are

carefully managed. Alternatively, the ground plane under the

ADC may contain serrations to steer currents in predictable

directions where cross coupling between analog and digital

would otherwise be unavoidable. The AD9225/AD9225EB

ground layout, shown in Figure 38, depicts the serrated type

of arrangement.

The board is built primarily over a common ground plane. It

has a slit to route currents near the clock driver. Figure 31 illus-

trates a general scheme of ground and power implementation, in

and around the AD9225.

ANALOG

CIRCUITS

DIGITAL

LOGIC

ICs

DVSS

AVSS

AVDD

DVDD

LOGIC

SUPPLY

VIN

CSTRAY

GND

= ANALOG

= DIGITAL

ADC

DIGITAL

CIRCUITS

Figure 31. Ground and Power Consideration

Analog and Digital Driver Supply Decoupling

The AD9225 features separate analog and driver supply and

ground pins, helping to minimize digital corruption of sensitive

analog signals. In general, AVDD, the analog supply, should

be decoupled to AVSS, the analog common, as close to the

chip as physically possible. Figure 32 shows the recommended

decoupling for the analog supplies; 0.1

mF ceramic chip and

mF tantalum capacitors should provide adequately low imped-

ance over a wide frequency range. Note that the AVDD and

AVSS pins are co-located on the AD9225 to simplify the layout

of the decoupling capacitors and provide the shortest possible

PCB trace lengths. The AD9225/AD9225EB power plane layout,

shown in Figure 39 depicts a typical arrangement using a multi-

layer PCB.

0.1 F

AVDD

AVSS

AD9225

10 F

Figure 32. Analog Supply Decoupling

The CML is an internal analog bias point used internally by

the AD9225. This pin must be decoupled with at least a 0.1

capacitor as shown in Figure 33. The dc level of CML is

approximately AVDD/2. This voltage should be buffered if it is

to be used for any external biasing.

0.1 F

CML

AD9225

Figure 33. CML Decoupling

Rev. C

AD9225ARSZRL Arkusz danych(PDF) 21 Page - Analog Devices

AD9225ARSZRL Arkusz danych(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Arkusz danych Pobierz

Link URL