ADAU1361BCPZ-R7 datasheet(54/81 Pages) AD

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ADAU1361

Rev. C | Page 53 of 80

R9: Right Differential Input Volume Control, 16,399 (0x400F)

This register enables the differential path and sets the volume control for the right differential PGA input.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RDVOL[5:0]

RDMUTE

RDEN

Table 36. Right Differential Input Volume Control Register

Bits

Bit Name

Description

[7:2]

RDVOL[5:0]

Right channel differential PGA input volume control. The right differential input uses the RINP (positive signal)

and RINN (negative signal) pins. Each step corresponds to a 0.75 dB increase in gain. See Table 71 for a complete

list of the volume settings.

Setting

Volume

000000

−12 dB (default)

000001

−11.25 dB

…

010000

0 dB

…

111110

34.5 dB

111111

35.25 dB

RDMUTE

Right differential input mute control.

0 = mute (default).

1 = unmute.

RDEN

Right differential PGA enable. When enabled, the RINP and RINN pins are used as a full differential pair. When

disabled, these two pins are configured as two single-ended inputs with the signals routed around the PGA.

0 = disabled (default).

1 = enabled.

R10: Record Microphone Bias Control, 16,400 (0x4010)

This register controls the MICBIAS pin settings for biasing electret type analog microphones.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

MPERF

MBI

Reserved

MBIEN

Table 37. Record Microphone Bias Control Register

Bits

Bit Name

Description

MPERF

Microphone bias is enabled for high performance or normal operation. High performance operation sources

more current to the microphone.

0 = normal operation (default).

1 = high performance.

MBI

Microphone voltage bias as a fraction of AVDD.

0 = 0.90 × AVDD (default).

1 = 0.65 × AVDD.

MBIEN

Enables the MICBIAS output.

0 = disabled (default).

1 = enabled.

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