AD7747_17 datasheet(10/29 Pages) AD

10 / 29 page

AD7747

Rev. 0 | Page 9 of 28

150

–150

01k

PARALLEL RESISTANCE (MΩ)

100

–50

–100

Figure 10. Capacitance Input Error vs. Parallel Resistance;

CIN(+) to GND = 8 pF, VDD = 5 V

–1000

200

CIN TO SHLD RESISTANCE (kΩ)

–100

–200

–300

–400

–500

–600

–700

–800

–900

100

125

150

175

Figure 11. Capacitance Input Error vs. Resistance Between CIN1(+) and SHLD;

CIN(+) to GND = 8 pF, VDD= 5 V

100

–1000

0.091

CIN TO SHLD RESISTANCE (MΩ)

–100

–200

–300

–400

–500

–600

–700

–800

–900

0.27

0.48

0.96

100

Figure 12. Capacitance Input Error vs. Resistance Between CIN(+) and SHLD;

CIN(+) to GND = 25 pF, VDD = 5 V

1.0

–1.0

0.01

100

SHLD TO GND RESISTANCE (MΩ)

0.1

1.0

10.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

Figure 13. Capacitance Input Error vs. Resistance Between SHLD and GND;

CIN(+) to GND = 8 pF; VDD = 5 V

–100

100

SERIAL RESISTANCE (kΩ)

–10

–20

–30

–40

–50

–60

–70

–80

–90

25 pF

8 pF

Figure 14. Capacitance Input Error vs. Serial Resistance;

CIN(+) to GND = 8 pF and 25pF, VDD = 5 V

0.2

–0.6

2.5

5.5

VDD (V)

–0.2

–0.4

3.0

3.5

4.0

4.5

5.0

Figure 15. Capacitance Input Power Supply Rejection (PSR);

CIN(+) to GND = 8 pF

AD7747 Arkusz danych(PDF) 10 Page - Analog Devices

AD7747 Arkusz danych(HTML) 10 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Arkusz danych Pobierz

Link URL