AD6677EBZ datasheet(44/48 Pages) AD

44 / 48 page

AD6677

Data Sheet

Rev. C | Page 44 of 48

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting system level design and layout of the AD6677, it

is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD6677, it is recommended that

two separate 1.8 V power supplies be used. The power supply

for AVDD can be isolated, and the power supply for DVDD and

DRVDD can be tied together, in which case, an isolation inductor

of approximately 1 µH is recommended. Alternatively, the

JESD204B PHY power (DRVDD) and analog (AVDD) supplies

can be tied together, and a separate supply can be used for the

digital outputs (DVDD).

The designer can employ several different decoupling capacitors

to cover both high and low frequencies. Place these capacitors

close to the point of entry at the PCB level and close to the pins

of the device with minimal trace length.

When using the AD6677, a single PCB ground plane is sufficient.

With proper decoupling and smart partitioning of the PCB analog,

digital, and clock sections, optimum performance is easily

achieved.

Exposed Pad Thermal Heat Slug Recommendations

It is mandatory that the exposed pad on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. Mate a continuous,

exposed (no solder mask) copper plane on the PCB to the

AD6677 exposed pad.

The copper plane must have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow

through the bottom of the PCB. Fill or plug these vias with

nonconductive epoxy.

To maximize the coverage and adhesion between the ADC and

the PCB, overlay a silkscreen to partition the continuous plane

on the PCB into several uniform sections. This provides several tie

points between the ADC and the PCB during the reflow process.

Using one continuous plane with no partitions guarantees only

one tie point between the ADC and the PCB. See the evaluation

board for a PCB layout example. For detailed information about

the packaging and PCB layout of chip scale packages, refer to

the Application Note AN-772, A Design and Manufacturing

Guide for the Lead Frame Chip Scale Package (LFCSP).

VCM

Decouple the VCM pin to ground with 0.1 µF capacitors, as shown

in Figure 31. It is recommended to place one 0.1 µF capacitor as

close as possible to the VCM pin and another at the VCM

connection to the analog input network.

SPI Port

Do not activate the SPI port during periods when the full dynamic

performance of the converter is required. Because the SCLK, CS,

and SDIO signals are typically asynchronous to the ADC clock,

noise from these signals can degrade converter performance. If the

on-board SPI bus is used for other devices, it may be necessary

to provide buffers between this bus and the AD6677 to keep these

signals from transitioning at the converter input pins during

critical sampling periods.

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