AD5662ARM datasheet(7/20 Pages) AD

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Preliminary Technical Data

AD5662

Rev. PrA | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTION

VDD 1

VREF 2

VFB 3

VOUT 4

GND

DIN

SCLK

SYNC

AD5662

TOP VIEW

(Not to Scale)

Figure 3. MSOP/SOT-23 Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Function

VDD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V. VDD should be decoupled to GND.

VREF

Reference Voltage Input.

VFB

Feedback Connection for the Output Amplifier.

VOUT

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

SYNC

Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.

The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the

rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz.

DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input.

GND

Ground Reference Point for All Circuitry on the Part.

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