5

SAM0358-052201

ESS Technology, Inc.

ES4428/ES4427 PRODUCT BRIEF

ES4427 PINOUT

Figure 2 shows the ES4427 device pinout.

Figure 2 ES4427 Device Pinout

ES4427 PIN DESCRIPTION

Table 2 lists the pin descriptions for the ES4427.

1

MIC1

MIC2

AOL+

AOL-

AOR-

AOR+

VCCAA

VREFP

VCM

VSSAA

AUX15/IR

AUX14

AUX13

RBCK/SER_IN

AUX12/C2PO

AUX11/IRQ

AUX10

RSD/SEL_PLL0

VCC

VSS

DSC_D7

HSYN_B

DSC_D6

VSYN_B

DSC_D5

YUV7

YUV6

YUV5

YUV4

VCC

VSS

YUV3

DSC_D4

YUV2

DSC_D3

YUV1

DSC_D2

YUV0

DSC_D1

VSS

31

30

51

50

80

81

100

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

ES4427

100-pin PQFP

Table 2

ES4427 Pin Descriptions

Name

Number

I/O

Definition

VSS

1, 25:26, 31, 72,

75, 77, 91, 100

I

Ground.

NC

2:4, 27:30, 76

No connect.

VCC

5, 16, 32, 66, 73, 78, 90

I

5.0V power supply.

DSC_C

6

I

Clock for programming to access internal registers.

AUX0

7

I/O

General purpose I/O.

DSC_D[7:0]

8, 81, 83, 85,

93, 95, 97, 99

I/O

Data for programming to access internal registers.

AUX1

9

I/O

General purpose I/O.

DSC_S

10

I

Strobe for programming to access internal registers.

AUX2

11

I/O

General purpose I/O.

DCLK

12

O

MPEG decoder output clock.

EXT_CLK

I

EXT_CLK is the external clock EXT_CLK is an input during bypass PLL mode.

RESET#

13

I

Reset.

AUX7

14

I/O

General purpose I/O.

MUTE

15

O

Audio mute.

MCLK

17

I

Audio master clock.