AD7666AST datasheet(21/29 Pages) AD

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AD7666

Rev. 0 | Page 20 of 28

For applications that use multiple AD7666s, it is more effective

to use the internal buffer to buffer the reference voltage.

Care should be taken with the voltage reference’s temperature

coefficient, which directly affects the full-scale accuracy if this

parameter matters. For instance, a ±15 ppm/°C temperature

coefficient of the reference changes full scale by ±1 LSB/°C.

Note that VREF can be increased to AVDD – 1.85 V. Since the

input range is defined in terms of VREF, this would essentially

increase the range to 0 V to 3 V with an AVDD above 4.85 V.

The AD780 can be selected with a 3 V reference voltage.

The TEMP pin, which measures the temperature of the

AD7666, can be used as shown in Figure 30. The output of

TEMP pin is applied to one of the inputs of the analog switch

(e.g., ADG779), and the ADC itself is used to measure its own

temperature. This configuration is very useful for improving the

calibration accuracy over the temperature range.

ADG779

AD8021

ANALOG INPUT

(UNIPOLAR)

AD7666

TEMPERATURE

SENSOR

TEMP

Figure 30. Temperature Sensor Connection Diagram

Power Supply

The AD7666 uses three power supply pins: an analog 5 V supply

AVDD, a digital 5 V core supply DVDD, and a digital input/

output interface supply OVDD. OVDD allows direct interface

with any logic between 2.7 V and DVDD + 0.3 V. To reduce the

supplies needed, the digital core (DVDD) can be supplied

through a simple RC filter from the analog supply, as shown in

Figure 26. The AD7666 is independent of power supply

sequencing once OVDD does not exceed DVDD by more than

0.3 V, and is thus free of supply voltage induced latch-up.

Additionally, it is very insensitive to power supply variations

over a wide frequency range, as shown in Figure 31, which

represents PSRR over frequency with on-chip and external

references.

INT REF

EXT REF

100

1000

10000

FREQUENCY (kHz)

Figure 31. PSRR vs. Frequency

POWER DISSIPATION VERSUS THROUGHPUT

Operating currents are very low during the acquisition phase,

allowing significant power savings when the conversion rate is

reduced (see Figure 32). The AD7666 automatically reduces its

power consumption at the end of each conversion phase. This

makes the part ideal for very low power battery applications.

The digital interface and the reference remain active even

during the acquisition phase. To reduce operating digital supply

currents even further, digital inputs need to be driven close to

the power supply rails (i.e., DVDD or DGND), and OVDD

should not exceed DVDD by more than 0.3 V.

100

10k

100

10k

100k

SAMPLING RATE (SPS)

PDREF = PDBUF = HIGH

100k

Figure 32. Power Dissipation vs. Sampling Rate

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