ICS93V855 datasheet(1/9 Pages) ICST

Numer części	ICS93V855

Szczegółowy opis	DDR Phase Lock Loop Clock Driver

PDF	9 Pages

Scroll/Zoom	100%

Producent	ICST [Integrated Circuit Systems]

Strona internetowa	http://www.icst.com

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1 / 9 page

Integrated

Circuit

Systems, Inc.

ICS93V855

0497B—06/01/04

Block Diagram

DDR Phase Lock Loop Clock Driver

Pin Configuration

Recommended Application:

DDR Clock Driver

Product Description/Features:

•

Low skew, low jitter PLL clock driver

•

External feedback pins for input to output

synchronization

•

Spread Spectrum tolerant inputs

•

With bypass mode mux

•

Operating frequency 60 to 170 MHz

Switching Characteristics:

•

CYCLE - CYCLE jitter:<75ps

•

OUTPUT - OUTPUT skew: <60ps

•

Output Rise and Fall Time: 650ps - 950ps

PLL

FB_INT

FB_INC

CLK_INC

CLK_INT

AVDD2.5

Control

Logic

FB_OUTT

FB_OUTC

DDRT0

DDRT1

DDRT2

DDRT3

DDRT4

DDRC0

DDRC1

DDRC2

DDRC3

DDRC4

Functionality

S

T

U

P

N

IS

T

U

P

T

U

O

e

t

a

t

S

L

P

D

V

AT

N

I

_

K

L

CC

N

I

_

K

L

CT

R

D

DC

R

D

DT

T

U

O

_

B

FC

T

U

O

_

B

F

D

N

GL

H

L

H

L

H

f

O

/

d

e

s

a

p

y

B

D

N

GH

L

H

L

H

L

f

O

/

d

e

s

a

p

y

B

V

5

.

2

)

m

o

n

(

LH

L

H

L

H

n

O

V

5

.

2

)

m

o

n

(

HL

H

L

H

L

n

O

V

5

.

2

)

m

o

n

(

z

H

M

0

2

<z

H

M

0

2

<Z

-

i

HZ

-

i

HZ

-

i

HZ

-

i

Hf

f

O

GND

1

28 DDRC4

DDRC0

2

27 DDRT4

DDRT0

3

26 VDD2.5

VDD2.5

4

25 GND

CLK_INT

5

24 FB_OUTC

CLK_INC

6

23 FB_OUTT

AVDD2.5

7

22 VDD2.5

AGND

8

21 FB_INT

GND

9

20 FB_INC

DDRC1 10

19 GND

DDRT1 11

18 VDD2.5

VDD2.5 12

17 DDRT3

DDRT2 13

16 DDRC3

DDRC2 14

15 GND

28-Pin 4.4mm TSSOP

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