IIS2DH datasheet(41/49 Pages) STMICROELECTRONICS

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IIS2DH

7.22

INT1_DURATION (33h)

The D[6:0] bits set the minimum duration of the interrupt 1 event to be recognized. Duration

steps and maximum values depend on the ODR chosen.

Duration time is measured in N/ODR, where N is the content of the duration register.

7.23

INT2_CFG (34h)

Table 57. INT1_THS description

THS[6:0]

Interrupt 1 threshold. Default value: 000 0000

1 LSb = 16 mg @ FS = 2 g

1 LSb = 32 mg @ FS = 4 g

1 LSb = 62 mg @ FS = 8 g

1 LSb = 186 mg @ FS = 16 g

Table 58. INT1_DURATION register

D6D5D4D3D2D1D0

Table 59. INT1_DURATION description

D[6:0]

Duration value. Default value: 000 0000

1 LSb = 1/ODR

Table 60. INT2_CFG register

AOI

ZHIE

ZLIE

YHIE

YLIE

XHIE

XLIE

Table 61. INT2_CFG description

AOI

AND/OR combination of interrupt events. Default value: 0

(see Table 62)

6-direction detection function enabled. Default value: 0. Refer to Table 62.

ZHIE

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

ZLIE

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

YHIE

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

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