MP8765 ─ 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

MP8765 Rev. 1.01

www.MonolithicPower.com

12

2/10/2015

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2015 MPS. All Rights Reserved.

As the output current increases from the light

load condition, the time period within which the

current modulator regulates becomes shorter.

The HS-FET is turned ON more frequently.

Hence,

the

switching

frequency

increases

correspondingly. The output current reaches the

critical level when the current modulator time is

zero. The critical level of the output current is

determined as follows:

IN

OUT

OUT

OUT

SW

IN

(V

V

) V

I

2L F

V

−×

=

××

×

(1)

It turns into PWM mode once the output current

exceeds the critical level. After that, the switching

frequency stays fairly constant over the output

current range.

PFM/PWM Mode Selection

The MP8765 has a MODE pin which provides

selectable operation mode for light load. Floating

the MODE pin or pulling it higher than 2V will set

MP8765 always work at force PWM mode.

Connecting MODE pin to ground enables PFM

(Pulse Frequency Modulation) mode at light load

condition. MP8765 skips some pulses for PFM

mode and achieves the light load power save.

Jitter and FB Ramp Slope

Jitter occurs in both PWM and skip modes when

noise in the VFB ripple propagates a delay to the

HS-FET driver, as shown in Figures 4 and 5.

Jitter can affect system stability, with noise

immunity proportional to the steepness of VFB’s

downward slope. However, VFB ripple does not

directly affect noise immunity.

V

RE F

V

FB

HS D river

J itter

V

S L O PE1

Figure 4—Jitter in PWM Mode

V

FB

HS D river

Jitter

V

REF

V

SL O P E 2

Figure 5—Jitter in Skip Mode

Operating without external ramp

The traditional constant-on-time control scheme

is intrinsically unstable if output capacitor’s ESR

is not large enough as an effective current-sense

resistor. Ceramic capacitors usually can not be

used as output capacitor.

To realize the stability, the ESR value should be

chosen as follow:

SW

ON

ESR

OUT

TT

0.7

2

R

C

+

×π

≥

(2)

The MP8765 has built in internal ramp

compensation to make sure the system is stable

even without the help of output capacitor’s ESR;

and thus the pure ceramic capacitor solution can

be applicant. The pure ceramic capacitor solution

can significantly reduce the output ripple, total

BOM cost and the board area.

Figure 6 shows a typical output circuit in PWM

mode without an external ramp circuit. Turn to

application information section for design steps

without external compensation.

R1

R2

ESR

CAP

SW

FB

Vo

L

Figure 6—Simplified Circuit in PWM Mode

without External Ramp Compensation