MP8765 ─ 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

MP8765 Rev. 1.01

www.MonolithicPower.com

13

2/10/2015

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When using a large-ESR capacitor on the output,

add a ceramic capacitor with a value of 10uF or

less to in parallel to minimize the effect of ESL.

Operating with external ramp compensation

The MP8765 is usually able to support ceramic

output capacitors without external ramp, however,

in some of the cases, the internal ramp may not

be enough to stabilize the system, and external

ramp

compensation

is

needed.

Skip

to

application information section for design steps

with external ramp compensation.

R1

R2

Ceramic

SW

FB

Vo

L

R4

C4

R9

Figure 7—Simplified Circuit in PWM Mode

with External Ramp Compensation

Figure 7 shows a simplified external ramp

compensation (R4 and C4) for PWM mode, with

HS-FET off. Chose R1, R2, R9 and C4 of the

external ramp to meet the following condition:

12

9

SW

4

1

2

RR

11

R

2F

C

5

R

R

⎛⎞

×

<×

+

⎜⎟

π×

×

+

⎝⎠

(3)

Where:

R4

C4

FB

C4

II

I

I

=+

≈

(4)

as:

IN

OUT

12

RAMP

ON

44

1

2

9

VV

R// R

VT

RC

R // R

R

−

=×

×

×+

(5)

follows

−

−

==

×

OUT

RAMP

SLOPE1

off

4

4

V

V

V

TR

C

(6)

As can be seen from equation 6, if there is

instability in PWM mode, we can reduce either

R4 or C4. If C4 can not be reduced further due to

limitation from equation 3, then we can only

reduce R4. For a stable PWM operation, the

SW

ON

-3

ESR

OUT

slope1

OUT

OUT

SW

on

TT

+-R

C

Io 10

0.7 π

2

-V

V

+

2L C

T -T

×

×

≥

××

(7)

Io is the load current.

ripple is the same whether the external ramp is

used or not. Figure 8 shows the simplified circuit

of the skip mode when both the HS-FET and LS-

FET are off.

R1

R2

ESR

Cout

FB

Vo

Ro

Figure 8—Simplified Circuit in skip Mode

mode can be determined as follow:

()

REF

SLOPE2

12

OUT

V

V

(R

R //Ro) C

−

=

+×

(8)

Where Ro is the equivalent load resistor.

As described in Figure 5, VSLOPE2 in the skip

mode is lower than that is in the PWM mode, so

it is reasonable that the jitter in the skip mode is

larger. If one wants a system with less jitter

during light load condition, the values of the VFB

resistors should not be too big, however, that will

decrease the light load efficiency.

Configuring the EN Control

EN is used to enable or disable the whole chip.

Pull En high to turn on the regulator and pull EN

low to turn it off. Do not float the pin.

For automatic start-up the EN pin can be pulled

up to input voltage through a resistive voltage

divider. Choose the values of the pull-up resistor

(Rup from Vin pin to EN pin) and the pull-down

resistor (Rdown from EN pin to GND) to

determine the automatic start-up voltage: