AD8375ACPZ-R7 datasheet(17/24 Pages) AD

17 / 24 page

Data Sheet

AD8375

Rev. B | Page 17 of 24

LAYOUT CONSIDERATIONS

There are two output pins for each polarity, and they are

oriented in an alternating fashion. When designing the board,

care should be taken to minimize the parasitic capacitance due

to the routing that connects the corresponding outputs together.

A good practice is to avoid any ground or power plane under

this routing region and under the chokes to minimize the

parasitic capacitance.

CHARACTERIZATION TEST CIRCUITS

Differential-to-Differential Characterization

The S-parameter characterization for the AD8375 was

performed using a dedicated differential input to differential

output characterization board. Figure 44 shows the layout of

characterization board. The board was designed for optimum

impedance matching into a 75 Ω system. Because both the

input and output impedances of the AD8375 are 150 Ω

differentially, 75 Ω impedance runs were used to match 75 Ω

network analyzer port impedances. On-board 1 μH inductors

were used for output biasing, and the output board traces were

designed for minimum capacitance.

0.1µF

1µH

0.1µF

+5V

A0 TO A4

Ω TRACES

Ω

AD8375

Figure 42. Test Circuit for S-Parameters on Dedicated 75 Ω

Differential-to-Differential Board

0.1µF

TC3-1T

0.1µF

330

Ω

330

Ω

+9V

A0 TO A4

Ω

AD8375

Figure 43. Test Circuit for Time Domain Measurements

Figure 44. Differential-to-Differential Characterization Board

Circuit Side Layout

0.1µF

TC3-1T

AD8375

1µH

0.1µF

Ω

ETC1-1-13

Ω

PAD LOSS = 11dB

+5V

A0 TO A4

Ω

Figure 45. Test Circuit for Distortion, Gain, and Noise

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