5

ATR0797

4665D–SIGE–08/04

1.10

Gain

Gain set = low;

GC1 = GC2 = 0

2-1,

16-15

G-7

-4

-2

dB

A

1.11

Input P1dB

1, 2,

15, 16

P1dB

12

14

dBm

C

1.12

DSB Noise figure

2-1,

16-15

NF

31

dB

D

2

I/Q Output

2.1

I/Q output frequency

range

1, 2,

15, 16

f

I/Q

DC

500

MHz

D

2.2

I/Q output amplitude

error

2-1,

16-15

-0.2

+0.2

dB

A

2.3

I/Q phase error

2-1,

16-15

-2

+2

deg

A

2.4

I/Q output common

mode voltage

1, 2,

15, 16

2.5

V

A

2.5

I/Q output differential

offset voltage

2-1,

16-15

-100

+100

mV

A

2.6

I/Q output return loss

50

Ω nominal

differential output

(3)

1, 2,

15, 16

RL

I/Q

20

dB

D

3

LO input

3.1

LO input level

13-12

P

LO

-3

0

+3

dBm

D

3.2

Return loss

13-12

RL

LO

20

dB

D

3.3

LO frequency range

13-12

RL

LO

65

300

MHz

D

4

Miscellaneous

4.1

Supply voltage

3, 7,

10, 14

V

CC

4.75

5

5.25

V

A

4.2

Supply current

3, 7,

10, 14

195

mA

A

4.3

GC1, GC2 logic level

low

4, 5

V

IL

0

0.3

×

V

CC

VD

4.4

GC1, GC2 logic level

high

4, 5

V

IH

0.7

×

V

CC

V

CC

VD

4.5

GC1, GC2 input

impedance

4, 5

Z

40

k

Ω

D

Electrical Characteristics (Continued)

Test conditions: V

IF input: at 200.1 MHz, GC1 = 0, GC2 = 0; 0 dBm

IF input: at 200.1 MHz, GC1 = 1, GC2 = 0; -20 dBm

IF input: at 200.1 MHz, GC1 = 1, GC2 = 1; -40 dBm

No.

Parameters

Test Conditions

Pin

Symbol

Min.

Typ.

Max.

Unit

Type

(1)

Notes:

1. Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

2. The parasitic inductance of the package, the board, and L5, L6 must be matched out at the center frequency with a series

capacitor to achieve 20 dB of port match.

3. The parasitic inductance of the package must be matched out to reach 20 dB port match above 100 MHz.