ISL6277HRZ datasheet(25/37 Pages) RENESAS

25 / 37 page

ISL6277

FN8270 Rev 1.00

Page 25 of 37

Mar 8, 2012

SVI Bus Protocol

The AMD processor bus protocol is compliant with SMBus send

byte protocol for VID transactions. The AMD SVD packet structure

is shown in Figure 19. The description of each bit of the three

bytes that make up the SVI command are shown in Table 8.

During a transaction, the processor sends the start sequence

followed by each of the three bytes which end with an optional

acknowledge bit. The ISL6277 does not drive the SVD line during

the ACK bit. Finally, the processor sends the stop sequence. After

the ISL6277 has detected the stop, it can then proceed with the

commanded action from the transaction.

Power States and Telemetry

SVI2 defines two power state indicator levels, see Table 9. As

processor current consumption reduces the power state indicator

level changes to improve VR efficiency under low power

conditions.

For the Core VR operating in 3-phase mode, when PSI0_L is

asserted Channels 2 & 3 are tri-stated and Channel 1 enters

diode emulation mode to boost efficiency. When PSI1_L is

asserted the Core VR continues to operate in this mode.

For the Northbridge VR operating in 2-phase mode, when PSI0_L

is asserted Channel 2 is tri-stated and Channel 1 enters diode

emulation mode to boost efficiency. When PSI1_L is asserted the

Core VR continues to operate in this fashion.

It is possible for the processor to assert or deassert PSI0_L and

PSI1_L out of order. PSI0_L takes priority over PSI1_L. If PSI0_L

is deasserted while PSI1_L is still asserted, the ISL6277 will

return the selected VR back full channel CCM operation.

The TFN bit along with the Core and Northbridge domain selector

bits are used by the processor to change the functionality of

telemetry, see Table 10 for more information.

FIGURE 19. SVD PACKET STRUCTURE

SVD

SVC

VID bits [7:1]

VID

bit [0]

ACK

TABLE 8. SVD DATA PACKET

BITS

DESCRIPTION

1:5 Always 11000b

Core domain selector bit, if set then the following data byte

contains VID, power state, telemetry control, load line trim and

offset trim apply to the Core VR.

Northbridge domain selector bit, if set then the following data

byte contains VID, power state, telemetry control, load line trim

and offset trim apply to the Northbridge VR.

8Always 0b

9Acknowledge Bit

PSI0_L

11:17 VID Code bits [7:1]

Acknowledge Bit

VID Code bit [0]

PSI1_L

TFN (Telemetry Functionality)

22:24 Load Line Slope Trim

25:26 Offset Trim [1:0]

Acknowledge Bit

TABLE 9. PSI0_L, PSI1_L AND TFN DEFINITION

FUNCTION

BIT

DESCRIPTION

PSI0_L

Power State Indicate level 0. When this signal is

asserted (active Low) the processor is in a low

enough power state for the ISL6277 to take action

to boost efficiency by dropping phases and entering

1-Phase DE.

PSI1_L

Power State Indicate level 1. When this signal is

asserted (active Low) the processor is in a low

enough power state for the ISL6277 to take action

to boost efficiency by dropping phases and entering

1-Phase DE.

TFN

Telemetry Functionality. This is an active high signal

that allows the processor to control the telemetry

functionality of the VR.

TABLE 10. TFN TRUTH TABLE

TFN, CORE, NB

BITS [21,6,7]

DESCRIPTION

1,0,1

Telemetry is in voltage and current mode. Therefore,

voltage and current are sent for VDD and VDDNB

domains by the controller.

1,0,0

Telemetry is in voltage mode only. Only the voltage of

VDD and VDDNB domains is sent by the controller.

1,1,0

Telemetry is disabled.

1,1,1

Reserved

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