ISL6277HRZ datasheet(26/37 Pages) RENESAS

26 / 37 page

ISL6277

FN8270 Rev 1.00

Page 26 of 37

Mar 8, 2012

Dynamic Load Line Slope Trim

The ISL6277 supports the SVI2 ability for the processor to

manipulate the load line slope of the Core and Northbridge VRs

independently using the serial VID interface. The slope

manipulation applies to the initial load line slope. A load line

slope trim will typically coincide with a VOTF change. See

Table 11 for more information about the load line slope trim

feature of the ISL6277.

Dynamic Offset Trim

The ISL6277 supports the SVI2 ability for the processor to

manipulate the output voltage offset of the Core and Northbridge

VRs. This offset is in addition to any output voltage offset set via

the COMP resistor reader. The dynamic offset trim can disable

the COMP resistor programmed offset of either output when

Disable All Offset’ is selected.

Protection Features

Core VR and Northbridge VR both provide overcurrent,

current-balance, undervoltage, and overvoltage fault protections.

The controller also provides over-temperature protection. The

following discussion is based on Core VR and also applies to the

Northbridge VR.

Overcurrent

Overcurrent protection is triggered when the voltage across the

IMON resistor is 1.5V. Within 2µs of detecting the IMON voltage,

the controller asserts VR_HOT_L low to communicate to the AMD

CPU to throttle back. A fault timer begins counting while IMON is at

or above the 1.5V threshold. The fault timer lasts 7.5µs to 11µs

and then flags an OCP fault. The controller then tri-states the

active channels and goes into shutdown. PGOOD is taken low and

a fault flag from this VR is sent to the other VR and it is shutdown

within 10µs. If the IMON voltage drops below the 1.5V threshold

prior to the fault timer count finishing, the fault timer is cleared

and VR_HOT_L is taken high.

The ISL6277 also features a way-overcurrent [WOC] feature which

immediately takes the controller into shutdown. This protection is

also referred to as fast overcurrent protection for short-circuit

protection. If the IMON current reaches 15µA, WOC is triggered.

Active channels are tri-stated and the controller is placed in

shutdown and PGOOD is pulled low. There is no fault timer on the

WOC fault, the controller takes immediate action. The other

controller output is also shutdown within 10µs.

Designing the current feedback components and setting the OCP

level require knowing the IDDSpike value (EDC) outlined for the

AMD CPU under consideration. AMD specifications will outline a

TDC current level and an EDC current level for each CPU. The EDC

current is the maximum current the CPU can demand for a short,

thermally insignificant time. When selecting the components for

the current feedback design or using an Intersil design

spreadsheet, the EDC current is used as the full load current. The

reasoning is that the AMD CPU will view reaching the EDC current

as 100% loading. The desired droop current at full load must be

set to 45μA. The controller generates a current across the IMON

resistor that is ¼ of the average value of the ISUM current. The

droop current is 5/4 greater than the ISUM current, so for a droop

current of 45μA the ISUM current is 36μA. The recommended

IMON resistor value is 133kΩ, 1% tolerance. At full load current,

EDC level, the resulting IMON voltage will be 1.2V and telemetry

will report 100%. If the load current continues to increase, then

the IMON voltage will continue to rise, but the telemetry will still

report 100% loading. Once the ISUM current reaches 45μA, the

corresponding current out of the IMON pin is 11.25μA and the

voltage on the IMON resistor will be 1.5V and the controller will

report an OC trip. The load current at this point is 25% higher

than the EDC current used for setting full load droop current. This

additional margin allows the AMD CPU to enter and exit the

IDDSpike performance mode without issue unless the load

current is out of line with the IDDSpike expectation.

Current-Balance

The controller monitors the ISENx pin voltages to determine

current-balance protection. If the ISENx pin voltage difference is

greater than 9mV for 1ms, the controller will declare a fault and

latch off.

Undervoltage

If the VSEN voltage falls below the output voltage VID value plus

any programmed offsets by -325mV, the controller declares an

undervoltage fault. The controller de-asserts PGOOD and

tri-states the power MOSFETs.

Overvoltage

If the VSEN voltage exceeds the output voltage VID value plus any

programmed offsets by +325mV, the controller declares an

overvoltage fault. The controller de-asserts PGOOD and turns on the

low-side power MOSFETs. The low-side power MOSFETs remain on

until the output voltage is pulled down below the VID set value. Once

the output voltage is below this level, the lower gate is tri-stated. If

the output voltage rises above the overvoltage threshold again, the

protection process is repeated. when all power MOSFETs are turned

off. This behavior provides the maximum amount of protection

against shorted high-side power MOSFETs while preventing output

ringing below ground.

TABLE 11. LOAD LINE SLOPE TRIM DEFINITION

LOAD LINE SLOPE TRIM [2:0]

DESCRIPTION

000

Disable LL

001

-40% mΩ Change

010

-20% mΩ Change

011

No Change

100

+20% mΩ Change

101

+40% mΩ Change

110

+60% mΩ Change

111

+80% mΩ Change

TABLE 12. OFFSET TRIM DEFINITION

OFFSET TRIM [1:0]

DESCRIPTION

Disable All Offset

-25mV Change

0mV Change

+25mV Change

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