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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADRF6518 Arkusz danych(PDF) 4 Page - Analog Devices |
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ADRF6518 Arkusz danych(HTML) 4 Page - Analog Devices |
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4 / 39 page  ADRF6518 Data Sheet Rev. A | Page 4 of 39 Parameter Test Conditions/Comments Min Typ Max Unit OUTPUT STAGE OPP1, OPM1, OPP2, OPM2, VOCM Maximum Output Swing At maximum gain, RLOAD = 400 Ω 3 V p-p HD2 > 65 dBc, HD3 > 65 dBc, RLOAD = 400 Ω 1.5 V p-p Differential Output Impedance <10 Ω Output DC Offset Inputs shorted, offset loop enabled <20 mV Output Common-Mode Range 1.5 V p-p output voltage 0.9 VPS − 1.2 V VOCM left floating VPS/2 V VOCM Input Impedance 23 kΩ NOISE/DISTORTION Corner Frequency = 63 MHz Output Noise Density Minimum gain at fc/2 −104.6 dBV/Hz Maximum gain at fc/2 −104.3 dBV/Hz Second Harmonic. HD2 16 MHz fundamental, 1.5 V p-p Output Level Gain = 6 dB 65 dBc Gain = 54 dB 65 dBc Third Harmonic, HD3 16 MHz fundamental, 1.5 V p-p Output Level Gain = 6 dB 82 dBc Gain = 54 dB 81 dBc IMD3 30 MHz and 31 MHz tones, 1.5 V p-p output level Gain = 0 dB 60 dBc Gain = 30 dB 80 dBc Gain = 60 dB 80 dBc DIGITAL LOGIC LE, CLK, DATA, SDO Input High Voltage, VHIGH >2 V Input Low Voltage, VLOW <0.8 V Input Current, IHIGH/ILOW <1 µA Input Capacitance, CIN 2 pF SPI TIMING LE, CLK, DATA, SDO fCLK 1/tCLK 20 MHz tDH DATA hold time 5 ns tDS DATA setup time 5 ns tLH LE hold time 5 ns tLS LE setup time 5 ns tPW CLK high pulse width 5 ns tD CLK to SDO delay 5 ns POWER AND ENABLE VPS, VPSD, COM, COMD, ENBL Supply Voltage Range 3.15 3.3 3.45 V Total Supply Current ENBL = 3.3 V Maximum BW setting, high power filter 400 mA Minimum BW setting, low power filter 360 mA Filter bypassed, high power mode 260 mA Filter bypassed, low power mode 230 mA Disable Current ENBL = 0 V, with pull-down resistors on output 1 mA Disable Threshold 1.6 V Enable Response Time Delay following ENBL low-to-high transition 20 µs Disable Response Time Delay following ENBL high-to-low transition 300 ns |
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