ADL5240ACPZ-R7 datasheet(18/28 Pages) AD

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ADL5240

Data Sheet

Rev. A | Page 18 of 28

SPI TIMING

Table 5 provides details aboutthe timing characteristics for the

SPI signals—namely, the clock(CLK), latch enable (LE), and

data (DATA)signals—and Figure 35 shows the corresponding

SPI timing diagram.

SPI Timing Sequence

Figure 36 is thetiming sequence fortheSPIfunction using a 6-bit

operation.Theclockcanbeas fast as20 MHz. In serialmode,

Table 4. Mode SelectionTable

Pin 32 (SEL)

Functionality

Connect to Ground

Serial mode

Connect to Supply

Parallel mode

Table 5. SPI TimingSetup

Parameter

Limit

Unit

Test Conditions/Comments

fCLK

MHz

Data clock frequency

ns min

Clock high time

ns min

Clock low time

ns min

Data to clock setup time

ns min

Clock to data hold time

ns min

Clock low to LE setup time

ns min

LE pulse width

DON'T CARE

MSB

CLK

DATA

LSB

Figure 35. SPI Timing Diagram (Data Is Loaded MSB First), Serial Mode

DON'T CARE

D2/LE

MSB

D0/CLK

D1/DATA

LSB

Figure 36. SPI Timing Sequence, Serial Mode

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