SSM4321ACBZ-R7 datasheet(15/24 Pages) AD

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Data Sheet

SSM4321

Rev. 0 | Page 15 of 24

EMI NOISE

The SSM4321 uses a proprietary modulation and spread-spectrum

technology to minimize EMI emissions from the device. For

applications that have difficulty passing FCC Class B emission tests

or experience antenna and RF sensitivity problems, the ultralow

EMI architecture of the SSM4321 significantly reduces the radiated

emissions at the Class-D outputs, particularly above 100 MHz.

EMI emission tests on the SSM4321 were performed in an FCC-

certified EMI laboratory with a 1 kHz input signal, producing

0.5 W of output power into an 8 Ω load from a 5.0 V supply. The

SSM4321 passed FCC Class B limits with 50 cm of unshielded

twisted pair speaker cable. Note that reducing the power supply

voltage greatly reduces radiated emissions.

OUTPUT CURRENT SENSING

The SSM4321 uses an external sense resistor to determine the

output current flowing to the load. As shown in Figure 1, one end

of the sense resistor is tied to one amplifier output pin (OUT+);

the other end of the sense resistor is tied to the load, which is also

connected to one sense input pin (SENSE−).

The voltage across the sense resistor is proportional to the load

current and is sent to an analog-to-digital converter (ADC) run-

ning nominally at 128 fS. The output of this ADC is downsampled

using digital filtering. The downsampled signal is output at a rate

of 8 kHz to 48 kHz on Slot 1 of the TDM bus. The 16-bit data is

in signed fractional format.

The current sense output is scaled so that an output current of

0.75 A (6 V/8 Ω) with a 200 mΩ sense resistor results in full-scale

output from the ADC. Table 7 lists the optimal sense resistor

values for commonly used output loads.

Table 7. Optimal Sense Resistor for Typical Loads

Load Value (Ω)

Peak Current (A)

Sense Resistor (mΩ)

0.75

200

1.5

100

OUTPUT VOLTAGE SENSING

The output voltage level is monitored and sent to an ADC

running nominally at 128 fS. The output of this ADC is down-

sampled using digital filtering. The downsampled signal is

output at a rate of 8 kHz to 48 kHz on Slot 2 of the TDM bus.

The 16-bit data is in signed fractional format.

PVDD SENSING

The SSM4321 contains an 8-bit ADC that measures the voltage

of the PVDD supply in real time. The output of the ADC is in

8-bit unsigned format and is presented on the 8 MSBs of Slot 3

on the TDM bus. The eight LSBs are driven low.

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