SSM4321ACBZ-R7 datasheet(16/24 Pages) AD

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SSM4321

Data Sheet

Rev. 0 | Page 16 of 24

SERIAL DATA INPUT/OUTPUT

The SSM4321 includes circuitry to sense output current, output

voltage, and the PVDD supply voltage. The output current, output

voltage, and PVDD voltage are sent to ADCs. The output of these

ADCs is available on the TDM or I2S output serial port. A direct

PDM bit stream of voltage and current data (or current and PVDD

data) can also be selected.

TDM OPERATING MODE

The digitized output current, output voltage, and PVDD sense

signals can be output on a TDM serial port. This serial port is

always a slave and requires a bit clock (BCLK) and a frame

synchronization signal (FSYNC) to operate. The output data is

driven on the SDATAO/PDM_DATA pin at the IOVDD voltage.

(See the Timing Diagrams, TDM Mode section.)

The FSYNC signal operates at the desired sample rate. A rising

edge of the FSYNC signal indicates the start of a new frame. For

proper operation, this signal should be one BCLK cycle wide,

transitioning on a falling BCLK edge. The MSB of the Slot 1 data

is output on the SDATAO/PDM_DATA pin one BCLK cycle later.

The SDATAO signal should be latched on a rising edge of BCLK.

Each slot is 64 BCLK cycles wide.

The SSM4321 can drive only four slots on its output, but it can

work with 8 slots, 12 slots, or 16 slots. In this way, up to four

SSM4321 devices can use the same TDM bus. At startup, the

number of slots used is recognized automatically by the number

of BCLK cycles between FSYNC pulses. Internal clocking is

automatically generated from BCLK based on the determined

BCLK rate.

The set of four TDM slots to be driven is determined by the

configuration of the SLOT pin on the SSM4321 (see Table 8).

The value of the SLOT pin must be stable at startup.

Table 8. TDM Slot Selection

Device Setting

SLOT Pin Configuration

TDM Slot 1 to Slot 4 used

Tie to IOVDD

TDM Slot 5 to Slot 8 used

Open

TDM Slot 9 to Slot 12 used

Tie to GND

TDM Slot 13 to Slot 16 used

Tie to IOVDD through a 47 kΩ resistor

The SSM4321 sets the SDATAO/PDM_DATA pin to a high

impedance state when a slot is present that is not being driven.

Connect a pull-down resistor to the SDATAO/PDM_DATA pin

so that it is always in a known state.

With a single SSM4321 operating with four slots, Slot 1 is for

the output current, Slot 2 is for the output voltage, Slot 3 is for

the PVDD supply, and Slot 4 is not driven. With more than four

slots, this pattern is repeated. Table 9 shows an example with

three SSM4321 devices and 12 TDM slots.

Table 9. TDM Output Slot Example—Three SSM4321 Devices

TDM Slot

Data Present

Output current, Device 1

Output voltage, Device 1

PVDD voltage, Device 1

High-Z

Output current, Device 2

Output voltage, Device 2

PVDD voltage, Device 2

High-Z

Output current, Device 3

Output voltage, Device 3

PVDD voltage, Device 3

High-Z

I2S AND LEFT JUSTIFIED OPERATING MODE

An I2S or left justified output interface can be selected by reversing

the pin connections for BCLK and FSYNC; that is, the I2S LRCLK

is connected to Ball D3 (BCLK_TDM/PDM_CLK/LRCLK_I2S),

and the I2S BCLK is connected to Ball D2 (FSYNC_TDM/

BCLK_I2S).

The I2S interface requires 64 BCLK cycles per LRCLK cycle. The

voltage information is sent when LRCLK is low, and the current

information is sent when LRCLK is high. (See the Timing

Diagrams, I2S and Left Justified Modes section.)

The SLOT pin configures the I2S or left justified output as follows

(see Table 10).

•

Selection of I2S or left justified mode.

•

Output of PVDD sense information. When PVDD data is

output, eight bits are appended to the 16-bit voltage sense

data to create a 24-bit output. The 16 MSBs represent the

voltage data; the eight LSBs represent the PVDD data.

•

Sample rate range. The sample rate ranges from 16 kHz

to 48 kHz. A range of 32 kHz to 48 kHz is also allowed in

low power I2S mode.

Table 10. I2S and Left Justified Slot Selection

Device Setting

BCLK Setting

SLOT Pin Configuration

I2S mode at 16 kHz to 48 kHz; voltage and current data only

64 × f

Tie to IOVDD

Left justified mode at 16 kHz to 48 kHz; voltage and current data only

64 × f

Open

I2S mode at 16 kHz to 48 kHz; PVDD data appended to voltage data

64 × f

Tie to GND

Left justified mode at 16 kHz to 48 kHz; PVDD data appended to voltage data

64 × f

Tie to IOVDD through a 47 kΩ resistor

Low power I2S mode at 32 kHz to 48 kHz; voltage and current data only

32 × f

S or 64 × fS

Tie to GND through a 47 kΩ resistor

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