AD8194

Data Sheet

Rev. A | Page 12 of 16

Both traces of a given differential pair must be equal in length

to minimize intrapair skew. Maintaining the physical symmetry

of a differential pair is integral to ensuring its signal integrity;

excessive intrapair skew can introduce jitter through duty

cycle distortion (DCD). The p and n of a given differential pair

should always be routed together to establish the required 100 Ω

differential impedance. Enough space should be left between

the differential pairs of a given group so that the n of one pair

does not couple to the p of another pair. For example, one tech-

nique is to make the interpair distance 4 to 10 times wider than

the intrapair spacing.

Any group of four TMDS channels (Input A, Input B, or the

output) should have closely matched trace lengths to minimize

interpair skew. Severe interpair skew can cause the data on the

four different channels of a group to arrive out of alignment

with one another. A good practice is to match the trace lengths

for a given group of four channels to within 0.05 inches on FR4

material.

The length of the TMDS traces should be minimized to reduce

overall signal degradation. Commonly used PC board material

such as FR4 is lossy at high frequencies; therefore, long traces

on the circuit board increase signal attenuation, resulting in

decreased signal swing and increased jitter through intersymbol

interference (ISI).

Controlling the Characteristic Impedance of a TMDS

Differential Pair

The characteristic impedance of a differential pair depends on a

number of variables, including the trace width, the distance

between the two traces, the height of the dielectric material

between the trace and the reference plane below it, and the

dielectric constant of the PCB binder material. To a lesser

extent, the characteristic impedance also depends upon the

trace thickness and the presence of solder mask.

There are many combinations that can produce the correct

characteristic impedance. It is generally required to work with

the PC board fabricator to obtain a set of parameters to produce

the desired results.

To guarantee a differential pair with a differential impedance of

100 Ω over the entire length of the trace, change the width of

the traces in a differential pair based on how closely one trace is

coupled to the other. When the two traces of a differential pair

are close and strongly coupled, they should have a width that

produces a 100 Ω differential impedance. When the traces split

apart to go into a connector, for example, and are no longer so

strongly coupled, the width of the traces should be increased to

yield a differential impedance of 100 Ω in the new configuration.

Ground Current Return

In some applications, it may be necessary to invert the output

pin order of the AD8194. This requires routing the TMDS

traces on multiple layers of the PCB. When routing differential

pairs on multiple layers, it is also necessary to reroute the

corresponding reference plane to provide one continuous

ground current return path for the differential signals. Standard

plated through-hole vias are acceptable for both the TMDS

traces and the reference plane. An example of this is illustrated

in Figure 21.

PCB DIELECTRIC

SILKSCREEN

SILKSCREEN

PCB DIELECTRIC

PCB DIELECTRIC

LAYER 2: GND (REFERENCE PLANE)

LAYER 4: SIGNAL (MICROSTRIP)

THROUGH-HOLE VIAS

LAYER 1: SIGNAL (MICROSTRIP)

KEEP REFERENCE PLANE

ADJACENT TO SIGNAL ON ALL

LAYERS TO PROVIDE CONTINUOUS

GROUND CURRENT RETURN PATH.

LAYER 3: PWR

(REFERENCE PLANE)

Figure 21. Example Routing of Reference Plane

TMDS Terminations

The AD8194 provides internal 50 Ω single-ended terminations

for all of its high speed inputs and outputs. The termination

resistors back-terminate the output TMDS transmission lines.

These back-terminations act to absorb reflections from imped-

ance discontinuities on the output traces, improving the signal

integrity of the output traces and adding flexibility to how the

output traces can be routed. For example, interlayer vias can be

used to route the AD8194 TMDS outputs on multiple layers of the

PCB without severely degrading the quality of the output signal.

In a typical application, the AD8194 output is connected to an

HDMI/DVI receiver or to another device with a 50 Ω single-ended

input termination. It is recommended that the outputs be

terminated with external 50 Ω on-board resistors when the

AD8194 is not connected to another device.