FUSB302MPX. datasheet(22/35 Pages) ONSEMI

22 / 35 page

www.fairchildsemi.com

FUSB302

• Rev. 2

www.onsemi.com

Table 10. Control0

Address: 06h

Reset Value: 0x0010_0100

Type: (see column below)

Bit #

Name

R/W/C Size (Bits)

Description

Reserved

N/A

Do Not Use

TX_FLUSH

W/C

1: Self clearing bit to flush the content of the transmit FIFO.

INT_MASK

R/W

1: Mask all interrupts.

0: Interrupts to host are enabled.

Reserved

N/A

Do Not Use

3:2

HOST_CUR[1:0]

R/W

1: Controls the host pull up current enabled by PU_EN[2:1]:

00: No current

01: 80 µA

– Default USB power.

10: 180 µA

– Medium Current Mode: 1.5 A

11: 330 µA

– High Current Mode: 3 A

AUTO_PRE

R/W

1: Starts the transmitter automatically when a message with a good

CRC is received. This allows the software to take as much as

300 µS to respond after the I_CRC_CHK interrupt is received.

Before starting the transmitter, an internal timer waits for

approximately 170 µS before executing the transmit start and

preamble.

0: Feature disabled.

TX_START

W/C

1: Start transmitter using the data in the transmit FIFO. Preamble is

started first. During the preamble period the transmit data can start

to be written to the transmit FIFO. Self clearing.

Table 11. Control1

Address: 07h

Reset Value: 0x0000_0000

Type: (see column below)

Bit #

Name

R/W/C Size (Bits)

Description

Reserved

N/A

Do Not Use

ENSOP2DB

R/W

Enable SOP”_DEBUG (SOP double prime debug) packets

0: Ignore SOP

”_DEBUG (SOP double prime debug) packets

ENSOP1DB

R/W

1: Enable SOP‘_DEBUG (SOP prime debug) packets

0: Ignore SOP

‘_DEBUG (SOP prime debug) packets

BIST_MODE2

R/W

1: Sent BIST Mode 01s pattern for testing

Reserved

N/A

Do Not Use

RX_FLUSH

W/C

1: Self clearing bit to flush the content of the receive FIFO.

ENSOP2

R/W

1: Enable SOP”(SOP double prime) packets

0: Ignore SOP

”(SOP double prime) packets

ENSOP1

R/W

1: Enable

SOP‘(SOP prime) packets

0: Ignore SOP

‘(SOP prime) packets

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