ADS5440IPFPR datasheet(5/11 Pages) TI

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TIMING CHARACTERISTICS

N+1

N+2

N+3

N+4

N−1

N−2

N−3

tsu_c

th_c

th_DR

N + 1

N + 2

N + 3

N + 4

tC_DR

tCLK

tCLKL

CLK, CLK

D[12:0],

OVR, OVR

DRY, DRY

AIN

tCLKH

tDR

tsu_DR

T0073-01

TIMING CHARACTERISTICS

ADS5440

SLAS467 – JULY 2005

Figure 1. Timing Diagram

over full temperature range, 50% clock duty cycle, sampling rate = 210 MSPS, AV

DD = 5 V, DRVDD = 3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperature delay

Clock slope independent aperature uncertainty (jitter)

Clock slope jitter factor dependency

s/V

Latency

cycles

Clock Input

tCLK

Clock period

4.76

tCLKH

Clock pulsewidth high

2.38

tCLKL

Clock pulsewidth low

2.38

Clock to DataReady (DRY)

tDR

Clock rising to DataReady falling

3.06

tC_DR

Clock rising to DataReady rising

Clock duty cycle = 50% (1)

5.44

Clock to DATA, OVR(2)

Data VOL to Data VOH (rise time)

Data VOH to Data VOL (fall time)

tsu_c

Data valid to clock (setup time)

0.64

th_c

Clock to invalid Data (hold time)

4.39

DataReady (DRY)/DATA, OVR(2)

tsu(DR)

Data valid to DRY

2.42

(1)

tC_DR = tDR + tCLKH for clock duty cycles other than 50%

(2)

Data is updated with clock rising edge or DRY falling edge.

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