LM2467 datasheet(38/43 Pages) NSC

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Pre-Amplifier Interface Registers (Continued)

Bit 5

When this bit is a 0, the full-scale outputs of DACs 1–3 are 0.5V to 4.5V. When it is a 1, the

full-scale level is 0.5V to 2.5V.

Bit 6

When this bit is a 0, the DAC 4 output is independent. When it is a 1, the DAC 4 output is scaled

by 50% and added to the outputs of DACs 1–3.

Bit 7

Reserved and should be set to zero.

Global Video Control:

GLOBALCTRL (0x8439)

Bank

Power

Blank

XXXXX

Bit 0

When this bit is a 1, the video outputs are blanked (set to black level). When it is a 0, video is not

blanked.

Bit 1

When this bit is a 1, the analog sections of the preamplifier are shut down for low power

consumption. When it is a 0, the analog sections are enabled.

Bits 7–3

Reserved.

Auxiliary Control:

AUXCTRL (0x843A)

Reserved

Horizontal Blank Position

H. Blank

Reserved

H Blnk

HBPOS[30]

HBPOS_EN

HBD

Bit 0

When this bit is a 0, the horizontal blanking input at pin 24 is gated to the video outputs to provide

horizontal blanking. When it is a 1, the horizontal blanking at the outputs is disabled.

Bit 1

Reserved

Bit 2

When this bit is a 1, the position of the Horizontal Blanking pulse can be programmably varied

relative to the horizontal flyback in number of pixels. When this bit is a 0, which is by default, the

horizontal blanking pulse position will not be programmable.

Bits 6–3

These 4 bits determine the position of the Horizontal Blanking Pulse with respect to the horizontal

flyback in number of pixels.

Bit 7

Reserved

PLL Range:

PLLFREQRNG (0x843E)

Res’d

PLL

Auto Mode

Clamp

Res’d

OSD

VBlank

PLL

Pre-calibration

PLL_AUTO

CLMP

OOR

VBL

PFR[1:0]

Bits 1–0

These bits must be set to 0 to pre-calibrate the PLL Auto feature.

Bit 2

This is the Vertical Blanking register. When this bit is a 1, vertical blanking is gated to the video outputs. When

set to a 0, the video outputs do not have vertical blanking.

Bit 3

This is the OSD override bit. This should be set to 0 for normal operation. When set to a 1, the video outputs

are disconnected and OSD only is displayed. This is useful for the OSD display of special conditions such as

“No Signal” and “Input Signal Out of Range”, to avoid seeing unsynchronized video.

Bit 4

Reserved and should be set to zero.

Bit 5

This is the Clamp Polarity bit. When set to a 0, the LM1236 expects a positive going clamp pulse. When set to

a 1, the expected pulse is negative going.

Bit 6

When this bit is set, the PLL Auto Mode will automatically determine the optimum frequency range of the

Phase Locked Loop.

Bit 7

Reserved and should be set to zero.

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