AD5541A datasheet(5/20 Pages) AD

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Data Sheet

AD5541A

Rev. B | Page 5 of 20

TIMING CHARACTERISTICS

VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, −40°C < TA < +105°C, unless otherwise

noted.

Table 4.

Parameter1,2

Limit at

1.8 ≤ VLOGIC ≤ 2.7 V

Limit at

2.7 V ≤ VLOGIC ≤ 5.5 V

Unit

Description

fSCLK

MHz max

SCLK cycle frequency

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

CS low to SCLK high setup

ns min

CS high to SCLK high setup

ns min

SCLK high to CS low hold time

ns min

SCLK high to CS high hold time

ns min

Data setup time

ns min

Data hold time (VINH = 90% of VDD, VINL = 10% of VDD)

ns min

Data hold time (VINH = 3 V, VINL = 0 V)

t10

ns min

LDAC pulse width

t11

ns min

CS high to LDAC low setup

t12

ns min

CS high time between active periods

Guaranteed by design and characterization. Not production tested.

All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.

SCLK

DIN

DB15

LDAC

t12

t11

t10

Figure 3. Timing Diagram

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