PSD813F1 datasheet(22/110 Pages) STMICROELECTRONICS

22 / 110 page

PSD813F1

22/110

READ

Under typical conditions, the microcontroller may

read the Flash or EEPROM memory using READ

operations just as it would a ROM or RAM device.

Alternately, the microcontroller may use READ op-

erations to obtain status information about a Pro-

gram or Erase operation in progress. Lastly, the

microcontroller may use instructions to read spe-

cial data from these memories. The following sec-

tions describe these READ functions.

Read Memory Contents. Main Flash is placed in

the READ mode after power-up, chip reset, or a

Reset Flash instruction (see Table 8., page 20).

The microcontroller can read the memory contents

of main Flash or EEPROM by using READ opera-

tions any time the READ operation is not part of an

instruction sequence.

Read Main Flash Memory Identifier. The main

Flash memory identifier is read with an instruction

composed of 4 operations:

3 specific write operations and a READ operation

(see Table 8). During the READ operation, ad-

dress bits A6, A1, and A0 must be 0,0,1, respec-

tively, and the appropriate sector select signal

(FSi) must be active. The Flash ID is E3h for the

PSD. The MCU can read the ID only when it is ex-

ecuting from the EEPROM.

Read Main Flash Memory Sector Protection

Status. The main Flash memory sector protection

status is read with an instruction composed of 4

operations: 3 specific WRITE operations and a

READ operation (see Table 8., page 20). During

the READ operation, address bits A6, A1, and A0

must be 0,1,0, respectively, while the chip select

FSi designates the Flash sector whose protection

has to be verified. The READ operation will pro-

duce 01h if the Flash sector is protected, or 00h if

the sector is not protected.

The sector protection status for all NVM blocks

(main Flash or EEPROM) can be read by the mi-

crocontroller accessing the Flash Protection and

PSD/EE Protection registers in PSD I/O space.

See

Flash

Memory

and

EEPROM

Sector

Protect, page 30 for register definitions.

Reading the OTP Row. There are 64 bytes of

One-Time-Programmable (OTP) memory that re-

side in EEPROM. These 64 bytes are in addition

to the 32 Kbytes of EEPROM memory. A READ of

the OTP row is done with an instruction composed

of at least 4 operations: 3 specific WRITE opera-

tions and one to 64 READ operations (see Table

8., page 20). During the READ operation(s), ad-

dress bit A6 must be zero, while address bits A5-

A0 define the OTP Row byte to be read while any

EEPROM sector select signal (EESi) is active. Af-

ter reading the last byte, an EEPROM Return in-

struction

must

executed

(see

Table

8., page 20).

Reading the Erase/Program Status Bits. The

PSD provides several status bits to be used by the

microcontroller to confirm the completion of an

erase or programming instruction of Flash memo-

ry. Bits are also available to show the status of

WRITES to EEPROM. These status bits minimize

the time that the microcontroller spends perform-

ing these tasks and are defined in Table 9. The

status bits can be read as many times as needed.

For Flash memory, the microcontroller can per-

form a READ operation to obtain these status bits

while an Erase or Program instruction is being ex-

ecuted by the embedded algorithm. See the sec-

tion

entitled

PROGRAMMING

FLASH

MEMORY, page 27 for details.

For EEPROM not in SDP mode, the microcontrol-

ler can perform a READ operation to obtain these

status bits just after a data WRITE operation. The

microcontroller may write one to 64 bytes before

reading the status bits. See the section entitled

Writing to the EEPROM, page 24 for details.

For EEPROM in SDP mode, the microcontroller

will perform a READ operation to obtain these sta-

tus bits while an SDP write instruction is being ex-

ecuted by the embedded algorithm. See section

entitled

EEPROM

Software

Data

Protect

(SDP), page 24 for details.

Table 9. Status Bit

Note: 1. X = not guaranteed value, can be read either 1 or 0.

2. DQ7-DQ0 represent the Data Bus Bits, D7-D0.

3. FSi and EESi are active High.

Device

FSi/

CSBOOTi

EESi

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Flash

VIH

VIL

Data Polling

Toggle

Flag

Error

Flag

Erase

Timeout

EEPROM

VIL

VIH

Data Polling

Toggle

Flag

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