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ADRF5730BCCZN-R7 Arkusz danych(PDF) 5 Page - Analog Devices

Numer części ADRF5730BCCZN-R7
Szczegółowy opis  Silicon Digital Attenuator
PDF  19 Pages
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ADRF5730BCCZN-R7 Arkusz danych(HTML) 5 Page - Analog Devices

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Data Sheet
ADRF5730
Rev. 0 | Page 5 of 19
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL CONTROL OUTPUT
D3/SEROUT pin2
Voltage
Low (VOUTL)
0 ± 0.3
V
High (VOUTH)
VDD ± 0.3
V
Current (IOUTL, IOUTH)
0.5
mA
SUPPLY CURRENT
VDD and VSS pins
Positive Supply Current
117
µA
Negative Supply Current
−117
µA
RECOMMENDED OPERATING
CONDITIONS
Supply Voltage
Positive (VDD)
3.15
3.45
V
Negative (VSS)
−3.45
−3.15
V
Digital Control Voltage
0
VDD
V
RF Input Power 3
f = 100 MHz to 30 GHz, TCASE = 85°C,4 all
attenuation states
ATTIN
Steady state average
27
dBm
Steady state peak
30
dBm
Hot switching average
24
dBm
Hot switching peak
27
dBm
ATTOUT (Bidirectional Use)
Steady state average
18
dBm
Steady state peak
21
dBm
Hot switching average
15
dBm
Hot switching peak
18
dBm
Case Temperature (TCASE)
−40
+105
°C
1
Input linearity performance degrades over frequency, see Figure 30 and Figure 31.
2
The D3/SEROUT pin is an input in parallel control mode and an output in serial control mode. See Table 5 for the pin function descriptions.
3
For power derating over frequency, see Figure 2 to Figure 3. Applicable for all ATTIN and ATTOUT power specifications.
4
For 105°C operation, the power handling degrades from the TCASE = 85°C specifications by 3 dB.
TIMING SPECIFICATIONS
See Figure 34, Figure 35, and Figure 36 for the timing diagrams.
Table 2.
Parameter
Description
Min
Typ
Max
Unit
tSCK
Minimum serial period, see Figure 34
70
ns
tCS
Control setup time, see Figure 34
15
ns
tCH
Control hold time, see Figure 34
20
ns
tLN
LE setup time, see Figure 34
15
ns
tLEW
Minimum LE pulse width, see Figure 34 and Figure 36
10
ns
tLES
Minimum LE pulse spacing, see Figure 34
630
ns
tCKN
Serial clock hold time from LE, see Figure 34
0
ns
tPH
Hold time, see Figure 36
10
ns
tPS
Setup time, see Figure 36
2
ns
tCO
Clock to output (SEROUT) time, see Figure 35
20
ns



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