ADRF5730BCCZN-R7 datasheet(14/19 Pages) AD

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ADRF5730

Data Sheet

Rev. 0 | Page 14 of 19

Figure 32. Simplified Circuit Diagram

SERIAL MODE INTERFACE

The ADRF5730 supports a 3-wire SPI: serial data input (SERIN),

clock (CLK), and latch enable (LE). The serial control interface

is activated when PS is set to high.

The ADRF5730 attenuation states can be controlled using 6-bit

or 8-bit SERIN data. If an 8-bit word is used to control the state

of the attenuator, the first two bits, D7 and D6, are don’t care

bits. It does not matter if these two bits are held low or high, or

if they are omitted altogether. Only Bits[D0:D5] set the state of

the attenuator.

In serial mode, the SERIN data is clocked most significant bit

(MSB) first on the rising CLK edges into the shift register. Then,

LE must be toggled high to latch the new attenuation state into

the device. LE must be set to low to clock new SERIN data into

the shift register as CLK is masked to prevent the attenuator

value from changing if LE is kept high. See Figure 34 in

conjunction with Table 2 and Table 7.

USING SEROUT

The ADRF5730 also features a serial data output, SEROUT.

SEROUT outputs the serial input data at the 8th clock cycle, and

can control a cascaded attenuator using a single SPI bus. Figure 35

shows the serial out timing diagram.

When using the attenuator in a daisy-chain operation, 8-bit

SERIN data must be used due to the 8 clock cycle delay between

SERIN and SEROUT.

It is optional to use a 1 kΩ resistor between SEROUT on the

first attenuator and SERIN of the next attenuator to filter the

signal (see Figure 33).

Figure 33. Using a Resistor on SEROUT

PARALLEL OR SERIAL SELECT

6-BIT OR 8-BIT LATCH

SERIN

CLK

INPUT

OUTPUT

SEROUT

0.5dB

1dB

2dB

4dB

8dB

16dB

200

100

300

400

500

150

250

350

450

TIME (ns)

WITHOUT 1kΩ

WITH 1kΩ

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