TMS27C020 262144 BY 8-BIT UV ERASABLE

TMS27PC020 262144 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997

3

POST OFFICE BOX 1443

read / output disable

When the outputs of two or more TMS27C020s or TMS27PC020s are connected in parallel on the same bus,

the output of any particular device in the circuit can be read with no interference from competing outputs of the

other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other

devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.

latchup immunity

Latchup immunity on the TMS27C020 and TMS72PC020 is a minimum of 250 mA on all inputs and outputs.

This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM

is interfaced to industry standard TTL or MOS logic devices. The input / output layout approach controls latchup

without compromising performance or packing density.

power down

100

µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.

erasure

Before programming, the TMS27C020 is erased by exposing the chip through the transparent lid to a high

intensity

ultraviolet

light

(wavelength

2537

Å).

The

recommended

minimum

exposure

dose

(UV intensity

21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are

in the high state. It should be noted that normal ambient light contains the correct wavelength for erasure.

Therefore, when using the TMS27C020, the window should be covered with an opaque label. After erasure (all

bits in logic high state), logic lows are programmed into the desired locations. A programmed low can be erased

only by ultraviolet light.

SNAP! Pulse programming

The TMS27C020 and TMS27PC020 are programmed using the TI SNAP! Pulse programming algorithm,

illustrated by the flowchart in Figure 1, which programs in a nominal time of twenty-six seconds. Actual

programming time varies as a function of the programmer used.

The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (

µs) followed by a byte

verification to determine when the addressed byte has been successfully programmed. Up to ten 100-

µs pulses

per byte are provided before a failure is recognized.

in parallel (eight bits) on pins DQ0 through DQ7. Once addresses and data are stable, PGM is pulsed low.

More than one device can be programmed when the devices are connected in parallel. Locations can be

programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with

program inhibit

Programming can be inhibited by maintaining a high level input on the E or PGM pins.

program verify

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode is

activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other

addresses must be held low. The signature code for the TMS27C020 is 9732. A0 low selects the manufacturer’s

code 97 ( Hex), and A0 high selects the device code 32 ( Hex), as shown in Table 3.