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CS7666 Arkusz danych(PDF) 13 Page - Cirrus Logic |
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CS7666 Arkusz danych(HTML) 13 Page - Cirrus Logic |
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13 / 42 page ![]() CS7666 DS302PP1 13 24.5454MHz CLKOUT DO [9-0] Line 3 Pixel 776 to Line 4 Pixel 3 DO [9-0] Line 263 Pixel 638 to Line 264 Pixel 645 DO [9-0] Line 525 Pixel 638 to Line 1 Pixel 645 Cb638 Y638 Cr638 Y639 FFh 00h 00h 9Dh 80h 10h 80h 10h 80h 10h EAV FFh 00h 00h F1h 80h 10h 80h 10h 80h 10h 80h 10h 80h 10h EAV FFh 00h 00h ABh 80h 10h 80h 10h 80h 10h 80h 10h 80h 10h SAV A A A NOTE: EAV, SAV, and Blanking data values are based on the 8 MSB’s of the output data, the two LSBs are considered fractional. Figure 5. 2x Pixel Clock, 10-Bit interleaved Output Format for 640x480 Image Format. 12.2727MHz CLKOUT HREF DO [9-0] DO [9-0] 10h Y0 Y1 Y2 Y3 Y4 Y633 Y634 Y635 Y636 Y637 Y638 Y639 10h 80h Cb0 Cr0 Cb2 Cr2 Cb4 Cb632 Cr634 Cb634 Cr636 Cb636 Cr638 Cb638 80h A B NOTE: EAV, SAV, and Blanking data values are based on the 8 MSB’s of the output data, the two LSBs are considered fractional. Figure 6. 1x Pixel Clock, 20-Bit Parallel Output Format for 640x480 Image Format. |
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