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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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LSM6DSR Arkusz danych(PDF) 12 Page - STMicroelectronics |
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LSM6DSR Arkusz danych(HTML) 12 Page - STMicroelectronics |
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12 / 168 page  4.4 Communication interface characteristics 4.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values (in mode 3) Symbol Parameter Value(1) Unit Min Max tc(SPC) SPI clock cycle 100 ns fc(SPC) SPI clock frequency 10 MHz tsu(CS) CS setup time 5 ns th(CS) CS hold time 20 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time 50 th(SO) SDO output hold time 5 tdis(SO) SDO output disable time 50 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production Figure 5. SPI slave timing diagram (in mode 3) Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both input and output ports. LSM6DSR Communication interface characteristics DS11976 - Rev 2 page 12/168 |
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