R7FA2L1AB2DFN datasheet(53/110 Pages) RENESAS

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Table 2.32

SPI timing (3 of 3)

Parameter

Symbol

Min

Max

Unit*1

Test

conditions

SPI MOSI and

MISO rise

and fall time

Output

2.7 V ≤ VCC ≤ 5.5 V

tDr, tDf

—

Figure 2.29

to Figure

2.34

C = 30 pF

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Input

—

µs

SSL rise and

fall time

Output

2.7 V ≤ VCC ≤ 5.5 V

tSSLr,

tSSLf

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Input

—

µs

Slave access time

2.4 V ≤ VCC ≤ 5.5 V

tSA

—

2 × tPcyc +

100

Figure 2.33

and Figure

2.34

C = 30 pF

1.8 V ≤ VCC < 2.4 V

—

2 × tPcyc +

140

1.6 V ≤ VCC < 1.8 V

—

2 × tPcyc +

180

Slave output release

time

2.4 V ≤ VCC ≤ 5.5 V

tREL

—

2 × tPcyc +

100

1.8 V ≤ VCC < 2.4 V

—

2 × tPcyc +

140

1.6 V ≤ VCC < 1.8 V

—

2 × tPcyc +

180

Note 1. tPcyc: PCLKB cycle.

Note 2. N is set as an integer from 1 to 8 by the SPCKD register.

Note 3. N is set as an integer from 1 to 8 by the SSLND register.

RSPCKn

master select

output

RSPCKn

slave select input

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

Note:

n = A or B

Figure 2.28

SPI clock timing

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

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