List of figures

Figure 1.

Logic diagram..................................................................... 2

Figure 2.

4-bump WLCSP connections .......................................................... 3

Figure 3.

Block diagram .................................................................... 5

Figure 4.

I2C bus protocol ................................................................... 7

Figure 5.

Write mode sequence SWP bit = 0 (data write enabled) ....................................... 10

Figure 6.

Write mode sequence with SWP bit = 1 (data write inhibited) ................................... 11

Figure 7.

Write cycle polling flowchart using ACK .................................................. 12

Figure 8.

Write on chip enable register ......................................................... 13

Figure 9.

Read mode sequences ............................................................. 14

Figure 10.

Read on chip enable register ......................................................... 16

Figure 11.

AC measurement I/O waveform ....................................................... 19

Figure 12.

Maximum Rbus value vs. bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . 23

Figure 13.

Maximum Rbus value vs. bus parasitic capacitance (Cbus) for an I2C bus at fC = 1MHz.................. 23

Figure 14.

AC waveforms ................................................................... 24

Figure 15.

Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, wafer level chip scale package outline.................. 25

Figure 16.

Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, with BSC, wafer level chip scale package outline .......... 27

Figure 17.

Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, wafer level chip scale recommended footprint ............ 28

M24128X-FCU

List of figures

DS12680 - Rev 2

page 34/35