LAN7430 datasheet(39/77 Pages) MICROCHIP

39 / 77 page

 2018-2019 Microchip Technology Inc.

DS00002631D-page 39

LAN7430/LAN7431

A signature of F3h indicates that the device is configured using values (MAC Address and subsequent as per EEPROM

Contents) from byte offset 1 in the OTP. A value of F7h indicates that the device is configured loading values (MAC

Address and subsequent as per EEPROM Contents) from byte offset 513 in the OTP.

As with the EEPROM, if a valid signature is not present at byte 0, the OTP shall be deemed to not be programmed and

the hardware shall not use it for configuring the device. Unlike the EEPROM, there is no signature value (e.g. AAh) that

indicates that only the MAC address is to be loaded.

6.10.2.2

Blank / No EEPROM

If A5h or AAh (EEPROM) or F3h or F7h (OTP) is not read from the first address, the EEPROM loader will end initializa-

tion. The device default values will be assumed unless a configured OTP is present.

Where there is no EEPROM or OTP, it is the responsibility of the Host LAN driver software to set the IEEE 802.3 address

by writing to the MAC Receive Address High Register (RX_ADDRH) and MAC Receive Address Low Register (RX_AD-

DRL).

6.11

One Time Programmable Memory (OTP)

The device integrates a 1K One Time Programmable (OTP) memory to store various configuration data and serve as

an EEPROM replacement to reduce bill of material costs. The OTP supports single bit writes and 8-bit reads. An

included OTP interrupt is available to indicate when the OTP is ready. The OTP provides a configurable standby mode

that reduces its power when operations have been completed.

OTP may potentially co-exist with an external EEPROM. Refer to Section 6.10.1, "EEPROM and OTP Relationship" for

additional details.

Certain system level resets may cause the OTP contents to be auto-loaded into the device. Refer to Section 6.10.2,

"EEPROM / OTP Auto-Load" for additional details.

6.12

Resets

The device provides the following chip-level reset sources:

• Power-On Reset (POR)

• External Chip Reset (RESET_N)

• PCIe Fundamental Reset

• Hot Resets

• Function-Level Reset (FLR)

• Soft Reset

• Soft-Lite Reset

• Power Management Soft Reset

Additionally, the device provides non-chip-level resets:

• Ethernet PHY Software Reset

• External PHY Reset

APPLICATION NOTE:

The dual signatures enable a mechanism for the OTP to be programmed twice. This may

prove useful for initial bring up of the device where inadvertently mis-programming the

device could render it non-functional. This scheme requires that when an signature of F3h

is used that only the first 512 bytes (0 through 511) of the OTP are programmed. In the

event that the OTP was mis-configured the device can be “saved” by changing the

signature on byte 0 from F3h to F7h and writing the new content starting at byte 513.

Note:

All OTP configuration is to be performed via the MPLAB Connect Configurator programming tool. Refer to

Section 5.2, "Programming Tools" for additional information.

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