MCP47FVB01A0T-ESLASHST datasheet(39/92 Pages) MICROCHIP

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DS20005405A-page 39

MCP47FVBXX

5.2

Voltage Reference Selection

The resistor ladder has up to four sources for the refer-

ence voltage. Two user control bits (VREF1:VREF0)

are used to control the selection, with the selection con-

nected to the VRL node (see Figures 5-3 and 5-4). The

four voltage source options for the Resistor Ladder are:

VDD pin voltage

Internal Voltage Reference (VBG)

VREF pin voltage unbuffered

VREF pin voltage internally buffered

The selection of the voltage is specified with the volatile

VREF1:VREF0 configuration bits (see Register 4-2). On

a POR/BOR event, the default configuration state is

latched into the volatile VREF1:VREF0 configuration

bits.

When the user selects the VDD as reference, the VREF

pin voltage is not connected to the resistor ladder.

If the VREF pin is selected, then select between the

buffered or unbuffered mode.

5.2.1

UNBUFFERED MODE

The VREF pin voltage may be from VSS to VDD.

5.2.2

BUFFERED MODE

The VREF pin voltage may be from 0.01V to VDD -

0.04V. The input buffer (amplifier) provides low offset

voltage, low noise, and a very high input impedance,

with only minor limitations on the input range and fre-

quency response.

FIGURE 5-3:

Resistor Ladder Reference

Voltage Selection Block Diagram.

FIGURE 5-4:

Reference Voltage Selection

Implementation Block Diagram.

5.2.3

BANDGAP MODE

If the Internal Band Gap is selected, then the external

VREF pin should not be driven and only use

high-impedance loads. Decoupling capacitors are

recommended for optimal operation.

The band gap output is buffered, but the internal

switches limit the current that the output should source

to the VREF pin. The resistor ladder buffer is used to

drive the Band Gap voltage for the cases of multiple

DAC outputs. This ensures that the resistor ladders are

always properly sourced when the band gap is selected.

Note 1:

The voltage source should have a low

output impedance. If the voltage source

has a high output impedance, then the

voltage on the VREF’s pin would be lower

than expected. The resistor ladder has a

typical impedance of 140 k

 and a typi-

cal capacitance of 29 pF.

If the VREF pin is tied to the VDD volt-

age, VDD mode (VREF1:VREF0 = ‘00’)

is recommended.

Note 1:

Any variation or noises on the reference

source can directly affect the DAC output.

The reference voltage needs to be as

clean as possible for accurate DAC

performance.

If the VREF pin is tied to the VDD volt-

age, VDD mode (VREF1:VREF0 = ‘00’)

is recommended.

VRL

VDD

Buffer

VREF1:VREF0

VREF

Band Gap

VREF

VDD

PD1:PD0 and

VREF1:VREF0

Band Gap (1)

(1.22V typical)

VDD

VREF1:VREF0

PD1:PD0

VRL

Note 1:

The Band Gap voltage (VBG) is 1.22V

typical. The band gap output goes through

the buffer with a 2x gain to create the VRL

voltage. See Section 5.4 “Internal Band

Gap”

for addition information on the band

gap circuit.

VREF1:VREF0

and BGEN

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