MCP47FVB01A0T-ESLASHST datasheet(40/92 Pages) MICROCHIP

40 / 92 page

MCP47FVBXX

DS20005405A-page 40

 2015 Microchip Technology Inc.

5.3

Output Buffer/VOUT Operation

The Output Driver buffers the wiper voltage (VW) of the

Resistor Ladder.

The DAC output is buffered with a low power and

precision output amplifier (op amp). This amplifier

provides a rail-to-rail output with low offset voltage and low

noise. The amplifier’s output can drive the resistive and

high-capacitive loads without oscillation. The amplifier

provides a maximum load current which is enough for

most programmable voltage reference applications. Refer

to Section 1.0 “Electrical Characteristics” for the

specifications of the output amplifier.

Figure 5-5 shows a block diagram of the output driver

circuit.

The user can select the output gain of the output

amplifier. Gain options are:

Gain of 1, with either VDD or VREF pin used as

reference voltage.

Gain of 2, only when VREF pin or Internal Band

Gap is used as reference voltage. The VREF pin

voltage should be limited to VDD/2.

Power-down logic also controls the output buffer oper-

ation (see Section 5.6 “Power-Down Operation” for

additional information on Power-down). In any of the

three Power-Down modes, the op amp is powered-

down and its output becomes a high impedance to the

VOUT pin.

Table 5-1 shows the gain bit operation. When the

reference voltage selection (VRL) is the device’s VDD

voltage, the G bit is ignored and a gain of 1 is used.

FIGURE 5-5:

Output Driver Block Diagram.

5.3.1

PROGRAMMABLE GAIN

The amplifier’s gain is controlled by the Gain (G)

configuration bit (see Register 4-4) and the VRL

reference selection (see Register 4-2). When the VRL

reference selection is the device’s VDD voltage, the G

bit is ignored and a gain of 1 is used.

The volatile G bit value can be modified by:

• POR event

• BOR event

•I2C Write commands

•I2C General Call Reset command

Note:

The load resistance must keep higher than

 for the stable and expected analog

output (to meet electrical specifications).

Gain(1)

VOUT

PD1:PD0

VDD

PD1:PD0

Note 1:

Gain options are 1x and 2x.

TABLE 5-1:

OUTPUT DRIVER GAIN

Gain Bit

Gain

Comment

Limits VREF pin voltages

relative to device VDD voltage.

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