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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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MCP48FVB22 Arkusz danych(PDF) 21 Page - Microchip Technology |
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MCP48FVB22 Arkusz danych(HTML) 21 Page - Microchip Technology |
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21 / 84 page  2015 Microchip Technology Inc. DS20005466A-page 21 MCP48FVBXX TABLE 1-3: SPI REQUIREMENTS (MODE = 11) SPI AC Characteristics Standard Operating Conditions (unless otherwise specified): Operating Temperature: -40 C TA +125C (Extended) Operating Voltage range is described in DC Characteristics. Param. No. Sym. Characteristic Min. Max. Units Conditions FSCK SCK input frequency — 10 MHz VDD = 2.7V to 5.5V (Read command) —20 MHz VDD = 2.7V to 5.5V (All other commands) —1 MHz VDD = 1.8V to 2.7V 70 TcsA2scH CS Active (VIL) to command’s 1st SCK input 60 — ns 71 TscH SCK input high time 20 — ns VDD = 2.7V to 5.5V 400 — ns VDD = 1.8V to 2.7V 72 TscL SCK input low time 20 — ns VDD = 2.7V to 5.5V 400 — ns VDD = 1.8V to 2.7V 73 TdiV2scH Setup time of SDI input to SCK edge 10 — ns 74 TscH2diL Hold time of SDI input from SCK edge 20 — ns 77 TcsH2DOZCS Inactive (VIH) to SDO output hi-impedance — 50 ns Note 1 80 TscL2doV SDO data output valid after SCK edge — 45 ns VDD = 2.7V to 5.5V — 170 ns VDD = 1.8V to 2.7V 83 TscH2csL CS Inactive (VIH) after SCK edge 100 — ns VDD = 2.7V to 5.5V 1µs VDD = 1.8V to 2.7V 84 TcsH CS high time (VIH) 50 — ns 94 TLATSU LAT to SCK ↑ (write data 24th bit) setup time 20 — ns Write Data transferred (4) 96 TLAT LAT high or low time 20 — ns 97 THVCSU HVC to SCK (1st data bit) (HVC setup time) 0— ns High-Voltage Commands (1) (MCP48FEBxx only) 98 THVCHD SCK ↑ (last bit of command (8th or 24th bit)) to HVC (HVC hold time) 25 — ns High-Voltage Commands (1) (MCP48FEBxx only) Note 1 This parameter is ensured by design. Note 4 The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK signal (Spec 94) or the current register data value may not be transferred to the output latch (VOUT) before the register is overwritten with the new value. |
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