Advanced Clock Drivers Devices

Freescale Semiconductor

3

MPC9850

Table 2. Function Table

Control

Default

0

1

REF_CLK_SEL

0

CLK

PCLK

REF_SEL

0

CLK or PCLK

XTAL

PLL_BYPASS

0

Normal

Bypass

REF_33MHz

0

Selects 25 MHz Reference

Selects 33 MHz Reference

MR

1

Reset

Normal

CLK_A, CLK_B, and RIO_C control output frequencies. See Table 3 and Table 4 for specific device configuration

Table 3. Output Configurations (Banks A & B)

1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)

CLK_x[0]

(msb)

CLK_x[1]

CLK_x[2]

CLK_x[3]

CLK_x[4]

CLK_x[5]

(lsb)

N

Frequency

(MHz)

111111

111111

126

15.87

111100

111100

120

16.67

101000

101000

80

25.00

011110

011110

60

33.33

010100

010100

40

50.00

001111

001111

30

66.67

001100

001100

24

83.33

001010

001010

20

100.00

001001

001001

18

111.11

001000

001000

16

125.00

000111

000111

15

133.33

000110

000110

12

166.67

000101

000101

10

200.00

000100

000100

2. Minimum value for N

250

Table 4. Output Configurations (Bank C)

RIO_C[0:1]

Frequency (MHz)

00

50 (test output)

01

125

10

250

11

500