VS6624P0LP datasheet(89/100 Pages) STMICROELECTRONICS

89 / 100 page

VS6624

Electrical characteristics

Rev 1

89/100

13.4

External clock

The VS6624 requires an external clock. This clock is a CMOS digital input. The clock input

is fail-safe in power down mode.

13.5

Chip enable

CE is a CMOS digital input. The module is powered down when a logic 0 is applied to CE.

See

Power up sequence for further information.

Table 46.

Typical current consumption - Sensor mode SXGA 15 fps

Symbol

Description

Test conditions

IAVDD

IVDD

Units

VDD = 2.8V VDD = 1.8V VDD = 2.8V

IPD

supply current in power

down mode

CE=0, CLK = 12 MHz

1.4

0.05

0.07

µA

Istanby

supply current in Standby

mode

CE=1, CLK = 12 MHz

0.0014

1.3

IStop

supply current in Stop

mode

CE=1, CLK = 12 MHz

0.0014

4.1

IPause

supply current in Pause

mode

CE=1, CLK = 12 MHz

0.0195

63.4

64.7

Irun

supply current in active

streaming run mode

CE=1, CLK = 12 MHz

streaming VGA @30 fps

11.5

84.5

Table 47.

External clock

CLK

Range

Unit

Min.

Typ.

Max.

DC coupled square wave

VDD

Clock frequency (normal operation)

6.50

6.50, 8.40, 9.60, 9.72, 12.00, 13.00,

16.80, 19.20, 19.44

MHz

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