VS6624P0LP datasheet(39/100 Pages) STMICROELECTRONICS

39 / 100 page

VS6624

Host communication - I²C control interface

Rev 1

39/100

10.5

Acknowledge

After every byte transferred the receiver must output an acknowledge bit. To acknowledge

the data byte receiver pulls SDA during the 9th SCL clock cycle generated by the master. If

SDA is not pulled low then the transmitter stops the output of data and releases control of

the bus back to the master so that it can either generate a STOP or a repeated START

condition.

Figure 24. Data acknowledge

10.6

Index space

Communication using the serial bus centres around a number of registers internal to the

either the sensor or the co-processor. These registers store sensor status, set-up, exposure

and system information. Most of the registers are read/write allowing the receiving

equipment to change their contents. Others (such as the chip id) are read only.

The internal register locations are organized in a 64k by 8-bit wide space. This space

includes “real” registers, SRAM, ROM and/or micro controller values.

START Condition

Negative Acknowledge (A)

Acknowledge (A)

Clock Pulse for Acknowledge

SDA data

transmitter

output by

SDA data

receiver

output by

SCL clock

from master

VS6624P0LP Arkusz danych(PDF) 39 Page - STMicroelectronics