ICS873033AMLF datasheet(8/16 Pages) ICST

8 / 16 page

873033AM

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 19, 2005

Integrated

Circuit

Systems, Inc.

ICS873033

HIGH SPEED, ÷4 DIFFERENTIAL-TO-

3.3V, 5V LVPECL/ECL CLOCK GENERATOR

APPLICATION INFORMATION

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

VCC

V_REF

0.1u

Single Ended Clock Input

PCLK

nPCLK

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

CC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

CC = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

Figure 3 shows an example of the differential input that can be

wired to accept single ended levels. The reference voltage level

BB generated from the device is connected to the negative

FIGURE 3. SINGLE ENDED LVPECL SIGNAL DRIVING

DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

input. The C1 capacitor should be located as close as possible

to the input pin.

PCLK

nPCLK

VBB

0.1u

CLK_IN

VCC

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