ADPA7005CHIP datasheet(15/23 Pages) AD

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Data Sheet

ADPA7005CHIP

Rev. 0 | Page 15 of 23

APPLICATIONS INFORMATION

The ADPA7005CHIP is a GaAs, pHEMT, MMIC power

amplifier. Capacitive bypassing is required for all VGGx and VDDx

pins (see Figure 51). VGG1 is the gate bias pad for the top

cascaded amplifiers. VGG2 is the gate bias pad for the bottom

cascaded amplifiers. VDD1, VDD3, and VDD5 are drain bias pads for

the top cascaded amplifiers. VDD2, VDD4, and VDD6 are drain bias

pads for the bottom cascaded amplifiers.

All measurements for this device were taken using the typical

application circuit (see Figure 63) and were configured as shown

in the assembly diagram (Figure 64).

The following is the recommended bias sequence during power-up:

1. Connect GND to RF and dc ground.

2. Set all gate bias voltages, VGG1 and VGG2, to −2 V.

3. Set all drain bias voltages, VDDxx, to 5 V.

4. Increase the gate bias voltage to achieve the quiescent

supply current and set IDQ, = 1200 mA.

5. Apply the RF signal.

The following is the recommended bias sequence during

power-down:

1. Turn off the RF signal.

2. Decrease the gate bias voltages, VGG1 and VGG2, to −2 V to

achieve an IDQ = 0 mA (approximately).

3. Decrease all drain bias voltages to 0 V.

4. Increase the VGG1 and VGG2 gate bias voltage to 0 V.

Figure 51. Simplified Block Diagram

Simplified bias pad connections to the dedicated gain stages and

dependence and independence among pads are shown in

Figure 51.

The VDD = 5 V and IDD = 1200 mA bias conditions are recom-

mended to optimize overall performance. Unless otherwise noted,

the data shown was taken using the recommended bias conditions.

Operation of the ADPA7005CHIP at different bias conditions may

provide performance that differs from what is shown in Figure 63

and Figure 64. Biasing the ADPA7005CHIP for higher drain

current typically results in higher P1dB, output IP3, and gain at the

expense of increased power consumption (see Table 7).

MOUNTING AND BONDING TECHNIQUES FOR

MILLIMETERWAVE GaAs MMICS

Attach the die directly to the ground plane with conductive

epoxy (see the Handling Precautions section, the Mounting

section, and the Wire Bonding section).

Microstrip, 50 Ω transmission lines on 0.127 mm thick alumina

thin film substrates are recommended for bringing the RF to

and from the chip. Raise the die 0.075 mm to ensure that the

surface of the die is coplanar with the surface of the substrate.

Place the microstrip substrates as close to the die as possible to

minimize ribbon bond length. Typical die to substrate spacing

is 0.076 mm to 0.152 mm. To ensure wideband matching, a

15 fF capacitive stub is recommended on the PCB before the

ribbon bond.

Figure 52. High Frequency Input Wideband Matching

Table 7. Power Selection Table1, 2

IDQ (mA)

Gain (dB)

P1dB (dBm)

OIP3 (dBm)

PDISS (W)

VGG (V)

1200

32.0

−0.59

1400

17.4

32.3

40.2

−0.53

1600

17.7

32.5

38.4

−0.46

Data taken at the following nominal bias conditions: VDD = 5 V, T = 25°C.

Adjust VGG1 and VGG2 from −2 V to 0 V to achieve the desired drain current.

VGG1

VGG2

VDD5

VDD3

VDD1

VDD6

VDD4

VDD2

RFOUT

RFIN

MMIC

PCB BOARD

50Ω

TRANSMISSION LINE

MATCHING STUB/BONDPAD

SHUNT CAPACITANCE = 15fF

3mil GOLD

RIBBON

3mil GAP

RFIN

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